Search Results - DaeYeal Lee

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  1. 1
    Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform

    Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform by Cheng, Chung-Kuan, Ho, Chia-Tung, Lee, Daeyeal, Lin, Bill

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  2. 2
    Multirow Complementary-FET (CFET) Standard Cell Synthesis Framework Using Satisfiability Modulo Theories (SMTs)

    Multirow Complementary-FET (CFET) Standard Cell Synthesis Framework Using Satisfiability Modulo Theories (SMTs) by Cheng, Chung-Kuan, Ho, Chia-Tung, Lee, Daeyeal, Lin, Bill

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  3. 3
    Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes

    Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes by Lee, Daeyeal, Ho, Chia-Tung, Kang, Ilgweon, Gao, Sicun, Lin, Bill, Cheng, Chung-Kuan

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  4. 4
    PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes

    PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes by Cheng, Chung-Kuan, Kahng, Andrew B., Kim, Hayoung, Kim, Minsoo, Lee, Daeyeal, Park, Dongwon, Woo, Mingyu

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  5. 5
    SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing

    SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing by Lee, Daeyeal, Lin, Bill, Cheng, Chung-Kuan

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  6. 6
    Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT

    Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT by Cheng, Chung-Kuan, Ho, Chia-Tung, Lee, Daeyeal, Lin, Bill, Park, Dongwon

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  7. 7
    Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis

    Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis by Cheng, Chung-Kuan, Ho, Chia-Tung, Holtz, Chester, Lee, Daeyeal, Lin, Bill

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  8. 8
    Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules

    Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules by Park, Dongwon, Lee, Daeyeal, Kang, Ilgweon, Holtz, Chester, Gao, Sicun, Lin, Bill, Cheng, Chung-Kuan

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  9. 9
    A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology

    A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology by Daeyeal Lee, Ik Joon Chang, Sang-Yong Yoon, Joonsuc Jang, Dong-Su Jang, Wook-Ghee Hahn, Jong-Yeol Park, Doo-Gon Kim, Chiweon Yoon, Bong-Soon Lim, Byung-Jun Min, Sung-Won Yun, Ji-Sang Lee, Il-Han Park, Kyung-Ryun Kim, Jeong-Yun Yun, Youse Kim, Yong-Sung Cho, Kyung-Min Kang, Sang-Hyun Joo, Jin-Young Chun, Jung-No Im, Seunghyuk Kwon, Seokjun Ham, Ansoo Park, Jae-Duk Yu, Nam-Hee Lee, Tae-Sung Lee, Moosung Kim, Hoosung Kim, Ki-Whan Song, Byung-Gil Jeon, Kihwan Choi, Jin-Man Han, Kye Hyun Kyung, Young-Ho Lim, Young-Hyun Jun

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  10. 10
    SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes

    SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes by Lee, Daeyeal, Park, Dongwon, Ho, Chia-Tung, Kang, Ilgweon, Kim, Hayoung, Gao, Sicun, Lin, Bill, Cheng, Chung-Kuan

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  11. 11
    SMT-Based Contention-Free Task Mapping and Scheduling on SMART NoC

    SMT-Based Contention-Free Task Mapping and Scheduling on SMART NoC by Lee, Daeyeal, Lin, Bill, Cheng, Chung-Kuan

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  12. 12
    Standard-Cell Scaling Framework with Guaranteed Pin-Accessibility

    Standard-Cell Scaling Framework with Guaranteed Pin-Accessibility by Cheng, Chung-Kuan, Lee, Daeyeal, Park, Dongwon

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  13. 13
    A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT

    A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT by Cheng, Chung-Kuan, Ho, Chia-Tung, Lee, Daeyeal, Park, Dongwon

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  14. 14
    CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation

    CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation by Cheng, Chung-Kuan, Kahng, Andrew B., Kang, Ilgweon, Kim, Minsoo, Lee, Daeyeal, Lin, Bill, Park, Dongwon, Woo, Mingyu

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  15. 15
    SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm

    SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm by Park, Dongwon, Lee, Daeyeal, Kang, Ilgweon, Gao, Sicun, Lin, Bill, Cheng, Chung-Kuan

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  16. 16
    An Effective Test Pattern Generation for Testing Signal Integrity

    An Effective Test Pattern Generation for Testing Signal Integrity by Yongjoon Kim, Myung-Hoon Yang, Youngkyu Park, DaeYeal Lee, Sungho Kang

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