On System-on-Chip Testing Using Hybrid Test Vector Compression by Biswas, Satyendra N., Das, Sunil R., Petriu, Emil M.

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Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation by Sakib, Mohammad Nazmus, Hassan, Rakibul, Biswas, Satyendra N., Das, Sunil R.

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Low-level logic fault testing ASIC simulation environment by Assaf, Mansour, Moore, Leslie-Ann, Das, Sunil, Biswas, Satyendra, Morton, Scott

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Energy efficient optimization of wireless embedded sensor networks by Assaf, Mansour, Khan, Salema, Das, Sunil, Biswas, Satyendra

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Response compression in space with cascade of two-input linear and nonlinear logic by Das, Sunil, Applegate, Alexander, Biswas, Satyendra, Petriu, Emil

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On automated test system for asymmetric digital subscriber line equipment by Syed, Tariq, Das, Sunil, Biswas, Satyendra, Assaf, Mansour, Petriu, Emil

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Cascade of two-input nonlinear logic in designing space compression networks in VLSI by Das, Sunil, Biswas, Satyendra, Groza, Voicu, Assaf, Mansour

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Fault-tolerance in VLSI systems design using data compression under constraints of failure probabilities-overview and current status by Das, Sunil, Biswas, Satyendra, Petriu, Emil, Groza, Voicu, Assaf, Mansour, Nayak, Amiya

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Implementing built-in self-test environment for cores-based digital circuits with Verilog HDL by Das, Sunil, Jin, Liwu, Assaf, Mansour, Biswas, Satyendra, Petriu, Emil

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An Optimized Tongue Drive System for Disabled Persons by Chand, Komal, Chand, Kavilash, Kumar, Rahul, Sharma, Bibhya, Assaf, Mansour H., Das, Sunil R., Groza, Voicu, Petriu, Emil M., Biswas, Satyendra N.

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Real Time Intelligent Traffic Light System by Prasad, Vijay, Uwais, Ali, Assaf, Mansour H., Das, Sunil R., Biswas, Satyendra N.

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An adaptive compressed MPEG-2 video watermarking scheme by Biswas, S., Das, S.R., Petriu, E.M.

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PGEN: A Novel Approach to Sequential Circuit Test Generation by Jone, Wen-Ben, Shah, Nigam, Gleason, Anita, Das, Sunil R.

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Designing Home Security and Monitoring System Based on Field Programmable Gate Array by Assaf, Mansour H., Mootoo, Ronald, Das, Sunil R., Petriu, Emil M., Groza, Voicu, Biswas, Satyendra N.

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Testing Analog and Mixed-Signal Circuits With Built-In Hardware-A New Approach by Das, S.R., Zakizadeh, J., Biswas, S., Assaf, M.H., Nayak, A.R., Petriu, E.M., Jone, W.-B., Sahinoglu, M.

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Getting errors to catch themselves - self-testing of VLSI circuits with built-in hardware by Das, S.R.

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Space compactor design in VLSI circuits based on graph theoretic concepts by Biswas, S., Das, S.R., Petriu, E.M.

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On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing by Das, S.R., Hossain, A., Biswas, S., Petriu, E.M., Assaf, M.H., Jone, W.-B., Sahinoglu, M.

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Guest Editorial Second Special Section of the IEEE Transactions on Instrumentation and Measurement in the Area of VLSI Testing-Future of Semiconductor Test by Das, S.R., Rajsuman, R.

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Test vector compression technique in system-on-chip by Biswas, Satyendra N, Das, Sunil R, Assaf, Mansour H, Hossain, Altaf

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