Search Results - Dasika, Ganesh S.

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  1. 1
    A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation

    A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation by Bull, D, Das, S, Shivashankar, K, Dasika, G S, Flautner, K, Blaauw, D

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  2. 2
    A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation

    A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation by Das, Shidhartha, Dasika, Ganesh S., Shivashankar, Karthik, Bull, David

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  3. 3
    Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation"

    Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation" by Bull, David, Das, Shidhartha, Shivashankar, Karthik, Dasika, Ganesh S., Flautner, Krisztian, Blaauw, David

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  4. 4
    Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache

    Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache by Ravindran, Rajiv A., Nagarkar, Pracheeti D., Dasika, Ganesh S., Marsman, Eric D., Senger, Robert M., Mahlke, Scott A., Brown, Richard B.

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  5. 5
    Partitioning variables across register windows to reduce spill code in a low-power processor

    Partitioning variables across register windows to reduce spill code in a low-power processor by Ravindran, R.A., Senger, R.M., Marsman, E.D., Dasika, G.S., Guthaus, M.R., Mahlke, S.A., Brown, R.B.

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  6. 6
    A 16-bit low-power microcontroller with monolithic MEMS-LC clocking

    A 16-bit low-power microcontroller with monolithic MEMS-LC clocking by Marsman, E. D., Senger, R. M., McCorquodale, M. S., Guthaus, Matthew R., Ravindran, Rajiv A., Dasika, Ganesh S., Mahlke, Scott A., Brown, Richard B.

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  7. 7
    A Customized Processor for Energy Efficient Scientific Computing

    A Customized Processor for Energy Efficient Scientific Computing by Sethia, A., Dasika, G., Mudge, T., Mahlke, S.

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  8. 8
    Compressing RNNs to Kilobyte Budget for IoT Devices Using Kronecker Products

    Compressing RNNs to Kilobyte Budget for IoT Devices Using Kronecker Products by Thakker, Urmish, Fedorov, Igor, Zhou, Chu, Gope, Dibakar, Mattina, Matthew, Dasika, Ganesh, Beu, Jesse

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  9. 9
    Guest Editors’ Introduction: Frontiers of Hardware and Algorithms for On-chip Learning

    Guest Editors’ Introduction: Frontiers of Hardware and Algorithms for On-chip Learning by Cao, Yu, Li, Xin, Seo, Jae-Sun, Dasika, Ganesh

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  10. 10
    Bridging the computation gap between programmable processors and hardwired accelerators

    Bridging the computation gap between programmable processors and hardwired accelerators by Fan, K., Kudlur, M., Dasika, G., Mahlke, S.

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  11. 11
    A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation

    A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation by Bull, D., Das, S., Shivshankar, K., Dasika, G., Flautner, K., Blaauw, D.

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  12. 12
    PEPSC: A Power-Efficient Processor for Scientific Computing

    PEPSC: A Power-Efficient Processor for Scientific Computing by Dasika, G., Sethia, A., Mudge, T., Mahlke, S.

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  13. 13
    A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation

    A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation by Das, Shidhartha, Dasika, Ganesh, Shivashankar, Karthik, Bull, David

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  14. 14
    Run-Time Efficient RNN Compression for Inference on Edge Devices

    Run-Time Efficient RNN Compression for Inference on Edge Devices by Thakker, Urmish, Beu, Jesse, Gope, Dibakar, Dasika, Ganesh, Mattina, Matthew

    Published in arXiv.org
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  15. 15
    DVFS in loop accelerators using BLADES

    DVFS in loop accelerators using BLADES by Dasika, Ganesh, Das, Shidhartha, Fan, Kevin, Mahlke, Scott, Bull, David

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  16. 16
    Ternary Hybrid Neural-Tree Networks for Highly Constrained IoT Applications

    Ternary Hybrid Neural-Tree Networks for Highly Constrained IoT Applications by Gope, Dibakar, Dasika, Ganesh, Mattina, Matthew

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  17. 17
    Rank and run-time aware compression of NLP Applications

    Rank and run-time aware compression of NLP Applications by Thakker, Urmish, Beu, Jesse, Gope, Dibakar, Dasika, Ganesh, Mattina, Matthew

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  18. 18
    Measuring scheduling efficiency of RNNs for NLP applications

    Measuring scheduling efficiency of RNNs for NLP applications by Thakker, Urmish, Dasika, Ganesh, Beu, Jesse, Mattina, Matthew

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  19. 19
    Compressing RNNs for IoT devices by 15-38x using Kronecker Products

    Compressing RNNs for IoT devices by 15-38x using Kronecker Products by Thakker, Urmish, Beu, Jesse, Gope, Dibakar, Chu, Zhou, Fedorov, Igor, Dasika, Ganesh, Mattina, Matthew

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  20. 20
    Pushing the limits of RNN Compression

    Pushing the limits of RNN Compression by Thakker, Urmish, Fedorov, Igor, Beu, Jesse, Gope, Dibakar, Chu, Zhou, Dasika, Ganesh, Mattina, Matthew

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