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A 1 GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration, and slew rate control
by
Plessas, F
,
Davrazos, E
,
Alexandropoulos, A
,
Birbas, M
,
Kikidis, J
Published in
Computers & electrical engineering
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A 1GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration, and slew rate control
by
Plessas, F.
,
Davrazos, E.
,
Alexandropoulos, A.
,
Birbas, M.
,
Kikidis, J.
Published in
Computers & electrical engineering
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A Novel 1.8 V, 1066 Mbps, DDR2, DFI-Compatible, Memory Interface
by
Alexandropoulos, A
,
Davrazos, E
,
Plessas, F
,
Birbas, M
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Computers & Electrical Engineering
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Calibration
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Backfile Package - Computer Science (Legacy) [Ycs]
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Elsevier Sd Backfile Engineering And Technology
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