Search Results - Di Spigna, Neil H

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  1. 1
    Scaling constraints in nanoelectronic random-access memories

    Scaling constraints in nanoelectronic random-access memories by Amsinck, Christian J, Di Spigna, Neil H, Nackashi, David P, Franzon, Paul D

    Published in Nanotechnology
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  2. 2
    Uniformity analysis of wafer scale sub-25nm wide nanowire array nanoimprint mold fabricated by PEDAL process

    Uniformity analysis of wafer scale sub-25nm wide nanowire array nanoimprint mold fabricated by PEDAL process by Sonkusale, Sachin R., Di Spigna, Neil H., Franzon, Paul D.

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  3. 3
    Fabrication of wafer scale, aligned sub-25 nm nanowire and nanowire templates using planar edge defined alternate layer process

    Fabrication of wafer scale, aligned sub-25 nm nanowire and nanowire templates using planar edge defined alternate layer process by Sonkusale, Sachin R., Amsinck, Christian J., Nackashi, David P., Di Spigna, Neil H., Barlage, Doug, Johnson, Mark, Franzon, Paul D.

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  4. 4
    Uniformity analysis of wafer scale sub-25 nm wide nanowire array nanoimprint mold fabricated by PEDAL process

    Uniformity analysis of wafer scale sub-25 nm wide nanowire array nanoimprint mold fabricated by PEDAL process by Sonkusale, Sachin R., Di Spigna, Neil H., Franzon, Paul D.

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  5. 5
    Deterministic nanowire fanout and interconnect without any critical translational alignment

    Deterministic nanowire fanout and interconnect without any critical translational alignment by Di Spigna, N.H., Nackashi, D.P., Amsinck, C.J., Sonkusale, S.R., Franzon, P.D.

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  6. 6
    Physically based molecular device model in a transient circuit simulator

    Physically based molecular device model in a transient circuit simulator by Kriplani, Nikhil M., Nackashi, David P., Amsinck, Christian J., Di Spigna, Neil H., Steer, Michael B., Franzon, Paul D., Rick, Ramon L., Solomon, Gemma C., Reimers, Jeffrey R.

    Published in Chemical physics
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  7. 7
    Fabrication of wafer scale, aligned sub-25nm nanowire and nanowire templates using planar edge defined alternate layer process

    Fabrication of wafer scale, aligned sub-25nm nanowire and nanowire templates using planar edge defined alternate layer process by Sonkusale, Sachin R., Amsinck, Christian J., Nackashi, David P., Di Spigna, Neil H., Barlage, Doug, Johnson, Mark, Franzon, Paul D.

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