Search Results - Diduck, Quentin

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  1. 1
    1.5-kV and 2.2-m \(\Omega \) -cm \(^\) Vertical GaN Transistors on Bulk-GaN Substrates

    1.5-kV and 2.2-m \(\Omega \) -cm \(^\) Vertical GaN Transistors on Bulk-GaN Substrates by Hui Nie, Diduck, Quentin, Alvarez, Brian, Edwards, Andrew P., Kayes, Brendan M., Ming Zhang, Gangfeng Ye, Prunty, Thomas, Bour, Dave, Kizilyalli, Isik C.

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  2. 2
    nand Gate Design for Ballistic Deflection Transistors

    nand Gate Design for Ballistic Deflection Transistors by Wolpert, David, Diduck, Quentin, Ampadu, Paul

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  3. 3
    3,000+ Hours continuous operation of GaN-on-Diamond HEMTs at 350°c channel temperature

    3,000+ Hours continuous operation of GaN-on-Diamond HEMTs at 350°c channel temperature by Ejeckam, Felix, Babic, Dubravko, Faili, Firooz, Francis, Daniel, Lowe, Frank, Diduck, Quentin, Khandavalli, Chandra, Twitchen, Daniel, Bolliger, Bruce

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  4. 4
    1000V Vertical JFET Using Bulk GaN

    1000V Vertical JFET Using Bulk GaN by Diduck, Quentin, Nie, Hui, Alvarez, Brian, Edwards, Andrew, Bour, David, Aktas, Ozgur, Disney, Don, Kizilyalli, Isik C.

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  5. 5
    Laser machining of GaN-on-diamond wafers

    Laser machining of GaN-on-diamond wafers by Babić, Dubravko I., Diduck, Quentin, Faili, Firooz, Wasserbauer, John, Lowe, Frank, Francis, Daniel, Ejeckam, Felix

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  6. 6
    A Terahertz Transistor Based on Geometrical Deflection of Ballistic Current

    A Terahertz Transistor Based on Geometrical Deflection of Ballistic Current by Diduck, Q., Margala, M., Feldman, M.J.

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  7. 7
    Ballistic deflection transistors and the emerging nanoscale era

    Ballistic deflection transistors and the emerging nanoscale era by Wolpert, D., Irie, H., Sobolewski, R., Ampadu, P., Diduck, Q., Margala, M.

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  8. 8
    Process tolerant calibration circuit for PLL applications with BIST

    Process tolerant calibration circuit for PLL applications with BIST by Diduck, Q., Liobe, J., Ali, S., Margala, M.

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  9. 9
    A new test methodology for DNL error in flash ADCs

    A new test methodology for DNL error in flash ADCs by Wieckowski, M., Liobe, J., Diduck, Q., Margala, M.

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  10. 10
    Performance optimization of room temperature Deflection Transistors through modified geometry

    Performance optimization of room temperature Deflection Transistors through modified geometry by Kaushal, V., Diduck, Q., Margala, M.

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  11. 11
    Terahertz Diode Development

    Terahertz Diode Development by Eastman, Lester F, Diduck, Quentin, Aslan, Barbaros

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  12. 12
    Nanotechnology based energy generation from thermal radiation

    Nanotechnology based energy generation from thermal radiation by Diduck, Q., Margala, M.

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