Search Results - Dobkin, Rostislav

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  1. 1
    Asynchronous Current Mode Serial Communication

    Asynchronous Current Mode Serial Communication by Dobkin, Rostislav, Moyal, Michael, Kolodny, Avinoam, Ginosar, Ran

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  2. 2
    QNoC asynchronous router

    QNoC asynchronous router by Dobkin, Rostislav (Reuven), Ginosar, Ran, Kolodny, Avinoam

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  3. 3
    StarSync: An extendable standard-cell mesochronous synchronizer

    StarSync: An extendable standard-cell mesochronous synchronizer by Verbitsky, Dmitry, Dobkin, Rostislav (Reuven), Ginosar, Ran, Beer, Salomon

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  4. 4
    Two-phase synchronization with sub-cycle latency

    Two-phase synchronization with sub-cycle latency by Dobkin, Rostislav (Reuven), Ginosar, Ran

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  5. 5
    High Rate Data Synchronization in GALS SoCs

    High Rate Data Synchronization in GALS SoCs by Dobkin, R., Ginosar, R., Sotiriou, C.P.

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  6. 6
    High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link

    High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link by Dobkin, R., Perelman, Y., Liran, T., Ginosar, R., Kolodny, A.

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  7. 7
    An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm

    An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm by Beer, Salomon, Ginosar, Ran, Priel, Michael, Dobkin, Rostislav, Kolodny, Avinoam

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  8. 8
    MTBF Estimation in Coherent Clock Domains

    MTBF Estimation in Coherent Clock Domains by Beer, S., Ginosar, R., Dobkin, R., Weizman, Y.

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  9. 9
    Fast asynchronous shift register for bit-serial communication

    Fast asynchronous shift register for bit-serial communication by Dobkin, R., Ginosar, R., Kolodny, A.

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  10. 10
    The Devolution of Synchronizers

    The Devolution of Synchronizers by Beer, Salomon, Ginosar, Ran, Priel, Michael, Dobkin, Rostislav, Kolodny, Avinoam

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  11. 11
    Data synchronization issues in GALS SoCs

    Data synchronization issues in GALS SoCs by Dobkin, R., Ginosar, R., Sotiriou, C.P.

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  12. 12
    Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders

    Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders by Dobkin, R., Peleg, M., Ginosar, R.

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  13. 13
    QNoC Asynchronous Router with Dynamic Virtual Channel Allocation

    QNoC Asynchronous Router with Dynamic Virtual Channel Allocation by Dobkin, R., Ginosar, R., Cidon, I.

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  14. 14
    An asynchronous router for multiple service levels networks on chip

    An asynchronous router for multiple service levels networks on chip by Rostislav, D., Vishnyakov, V., Friedman, E., Ginosar, R.

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  15. 15
    The devolution of synchronizers

    The devolution of synchronizers by Beer, Salomon, Ginosar, Ran, Priel, Michael, Dobkin, Rostislav, Kolodny, Avinoam

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  16. 16
    Near-threshold 40nm Supply Feedback C-element

    Near-threshold 40nm Supply Feedback C-element by Schwartz, I., Teman, A., Dobkin, R., Fish, A.

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  17. 17
    Implementation of interference rejection for OFDM communications

    Implementation of interference rejection for OFDM communications by Tamam, Ariel, Dobkin, Rostislav, Maltz, Ofer, Zahavi, Lior, Pecht, Efraim, Peleg, Michael

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  18. 18
    Parallel VLSI architecture for MAP turbo decoder

    Parallel VLSI architecture for MAP turbo decoder by Dobkin, R., Peleg, M., Ginosar, R.

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