Silicon CMOS devices beyond scaling by Haensch, W., Nowak, E. J., Dennard, R. H., Solomon, P. M., Bryant, A., Dokumaci, O. H., Kumar, A., Wang, X., Johnson, J. B., Fischetti, M. V.

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Artificial Intelligence in Early Diagnosis of Preeclampsia by Bülez, A, Hansu, K, Çağan, ES, Şahin, AR, Dokumacı, HÖ

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Optimizing CMOS technology for maximum performance by Frank, D J, Haensch, W, Shahidi, G, Dokumaci, O H

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Optimizing CMOS technology for maximum performance by Frank, D J, Haensch, W, Shahidi, G, Dokumaci, O H

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Existence of SARS-CoV-2 RNA on ambient particulate matter samples: A nationwide study in Turkey by Kayalar, Özgecan, Arı, Akif, Babuççu, Gizem, Konyalılar, Nur, Doğan, Özlem, Can, Füsun, Şahin, Ülkü A., Gaga, Eftade O., Levent Kuzu, S., Arı, Pelin Ertürk, Odabaşı, Mustafa, Taşdemir, Yücel, Sıddık Cindoruk, S., Esen, Fatma, Sakın, Egemen, Çalışkan, Burak, Tecer, Lokman H., Fıçıcı, Merve, Altın, Ahmet, Onat, Burcu, Ayvaz, Coşkun, Uzun, Burcu, Saral, Arslan, Döğeroğlu, Tuncay, Malkoç, Semra, Üzmez, Özlem Özden, Kunt, Fatma, Aydın, Senar, Kara, Melik, Yaman, Barış, Doğan, Güray, Olgun, Bihter, Dokumacı, Ebru N., Güllü, Gülen, Uzunpınar, Elif S., Bayram, Hasan

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FinFET performance advantage at 22nm: An AC perspective by Guillorn, M., Chang, J., Bryant, A., Fuller, N., Dokumaci, O., Wang, X., Newbury, J., Babich, K., Ott, J., Haran, B., Yu, R., Lavoie, C., Klaus, D., Zhang, Y., Sikorski, E., Graham, W., To, B., Lofaro, M., Tornello, J., Koli, D., Yang, B., Pyzyna, A., Neumeyer, D., Khater, M., Yagishita, A., Kawasaki, H., Haensch, W.

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An experimental study on transport issues and electrostatics of ultrathin body SOI pMOSFETs by Ren, Z., Hegde, S., Doris, B., Oldiges, P., Kanarsky, T., Dokumaci, O., Roy, R., Leong, M., Jones, E.C., Wong, H.-S.P.

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Left anterior descending coronary artery occlusion after left lateral free wall accessory pathway ablation: what is the possible mechanism? by Dinckal, H, Yucel, O, Kirilmaz, A, Karaca, M, Kilicaslan, F, Dokumaci, B

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Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETs by Nayfeh, H.M., Singh, D.V., Hergenrother, J.M., Sleight, J.W., Ren, Z., Dokumaci, O., Black, L., Chidambarrao, D., Venigalla, R., Pan, J., Natzle, W., Tessier, B.L., Ott, J.A., Khare, M., Guarini, K.W., Ieong, M., Haensch, W.

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Detection of the Defibrillation Threshold Using the Upper Limit of Vulnerability Following Defibrillator Implantation by KIRILMAZ, ATA, DOKUMACI, BARBAROS, UZUN, MEHMET, KILICASLAN, FETHI, DINCKAL, M. HAKAN, YUCEL, OZCAN, KARACA, MUSTAFA

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Nitrogen-induced transient enhanced diffusion of dopants by Murthy, Cheruvu, Lee, Kilho, Rengarajan, Rajesh, Dokumaci, Omer, Ronsheim, Paul, Tews, Helmut, Inaba, Satoshi

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Two gates are better than one [double-gate MOSFET process] by Solomon, P.M., Hovel, H.J., Bucchignano, J.J., Cabral, C., Lavoie, C., Ku, V., Boyd, D.C., Petrarca, K., Yoon, J.H., Babich, I.V., Treichler, J., Guarini, K.W., Kozlowski, P.M., Newbury, J.S., D'Emic, C.P., Sicina, R.M., Benedict, J., Wong, H.-S.P., Zhang, Y., Chan, K., Jones, E.C., Cohen, G.M., Krasnoperova, A., Ronay, M., Dokumaci, O.

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Extreme scaling with ultra-thin Si channel MOSFETs by Doris, B., Meikei Ieong, Kanarsky, T., Ying Zhang, Roy, R.A., Dokumaci, O., Zhibin Ren, Fen-Fen Jamin, Leathen Shi, Natzle, W., Hsiang-Jen Huang, Mezzapelle, J., Mocuta, A., Womack, S., Gribelyuk, M., Jones, E.C., Miller, R.J., Wong, H.-S.P., Haensch, W.

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Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths by Singh, D.V., Hergenrother, J.M., Sleight, J.W., Ren, Z., Nayfeh, H., Dokumaci, O., Black, L., Chidambarrao, D., Venigalla, R., Pan, J., Tessier, B.L., Nomura, A., Ott, J.A., Khare, M., Guarini, K.W., Ieong, M., Haensch, W.

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Examination of hole mobility in ultra-thin body SOI MOSFETs by Zhibin Ren, Solomon, P.M., Kanarsky, T., Doris, B., Dokumaci, O., Oldiges, P., Roy, R.A., Jones, E.C., Meikei Ieong, Miller, R.J., Haensch, W., Wong, H.-S.P.

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Two gates are better than one - double-gate MOSFET process by Solomon, P M, Guarini, K W, Zhang, Y, Chan, K, Jones, E C, Cohen, G M, Krasnoperova, A, Ronay, M, Dokumaci, O, Hovel, H J, Bucchignano, J J, Cabral, C, Lavoie, C, Ku, V, Boyd, D C, Petrarca, K, Yoon, J H, Babich, I V, Treichler, J

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Triple-self-aligned, planar double-gate MOSFETs: devices and circuits by Guarini, K.W., Solomon, P.M., Zhang, Y., Chan, K.K., Jones, E.C., Cohen, G.M., Krasnoperova, A., Ronay, M., Dokumaci, O., Bucchignano, J.J., Cabral, C., Lavoie, C., Ku, V., Boyd, D.C., Petrarca, K.S., Babich, I.V., Treichler, J., Kozlowski, P.M., Newbury, J.S., D'Emic, C.P., Sicina, R.M., Wong, H.-S.

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Selective epitaxial channel ground plane thin SOI CMOS devices by Zhibin Ren, Ieong, M., Cai, J., Holt, J., Boyd, D., Mo, R., Yin, H., Dokumaci, O., Kawanaka, S., Sato, T., Ronsheim, P., Wang, J., Sung, C.Y., Haensch, W.

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Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths by Singh, D.V., Sleight, J.W., Hergenrother, J.M., Ren, Z., Jenkins, K.A., Dokumaci, O., Black, L., Chang, J.B., Nakayama, H., Chidambarrao, D., Venigalla, R., Pan, J., Natzle, W., Tessier, B.L., Nomura, A., Ott, J.A., Ieong, M., Haensch, W.

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Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOSFETs by Ieong, M., Jones, E.C., Kanarsky, T., Ren, Z., Dokumaci, O., Roy, R.A., Shi, L., Furukawa, T., Taur, Y., Miller, R.J., Wong, H.-S.P.

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