Search Results - Drazdziulis, M.

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  1. 1
    A low-leakage twin-precision multiplier using reconfigurable power gating

    A low-leakage twin-precision multiplier using reconfigurable power gating by Sjalander, M., Drazdziulis, M., Larsson-Edefors, P., Eriksson, H.

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  2. 2
    A gate leakage reduction strategy for future CMOS circuits

    A gate leakage reduction strategy for future CMOS circuits by Drazdziulis, M., Larsson-Edefors, P.

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  3. 3
    Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration

    Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration by Do, Minh Q., Drazdziulis, Mindaugas, Larsson-Edefors, Per, Bengtsson, Lars

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  4. 4
    A power cut-off technique for gate leakage suppression [CMOS logic circuits]

    A power cut-off technique for gate leakage suppression [CMOS logic circuits] by Drazdziulis, M., Larsson-Edefors, P., Eckerbert, D., Eriksson, H.

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  5. 5
    Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays

    Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays by Do, M.Q., Drazdziulis, M., Larsson-Edefors, P., Bengtsson, L.

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  6. 6
    Overdrive Power-Gating Techniques for Total Power Minimization

    Overdrive Power-Gating Techniques for Total Power Minimization by Drazdziulis, M., Larsson-Edefors, P., Svensson, L.

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