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A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining
by
Barth, J.E.
,
Anand, D.
,
Burns, S.
,
Dreibelbis, J.H.
,
Fifield, J.A.
,
Gorman, K.
,
Nelms, M.
,
Nelson, E.
,
Paparelli, A.
,
Pomichter, G.
,
Pontius, D.E.
,
Sliva, S.
Published in
IEEE journal of solid-state circuits
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Ieee Journal Of Solid-State Circuits
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