Search Results - EARLIE, Eugene

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  1. 1
    Register File Power Reduction Using Bypass Sensitive Compiler

    Register File Power Reduction Using Bypass Sensitive Compiler by Sanghyun Park, Shrivastava, A., Dutt, N., Nicolau, A., Yunheung Paek, Earlie, E.

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  2. 2
    Automatic Design Space Exploration of Register Bypasses in Embedded Processors

    Automatic Design Space Exploration of Register Bypasses in Embedded Processors by Shrivastava, A., Park Sanghyun, Earlie, E., Dutt, N.D., Nicolau, A., Paek Yunheung

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  3. 3
    Retargetable pipeline hazard detection for partially bypassed processors : Hardware/software codesign and system synthesis II

    Retargetable pipeline hazard detection for partially bypassed processors : Hardware/software codesign and system synthesis II by SHRIVASTAVA, Aviral, EARLIE, Eugene, DUTT, Nikil D, NICOLAU, Alex

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  4. 4
    Retargetable pipeline hazard detection for partially bypassed processors

    Retargetable pipeline hazard detection for partially bypassed processors by Shrivastava, A., Earlie, E., Dutt, N.D., Nicolau, A.

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  5. 5
    PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors

    PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors by Shrivastava, Aviral, Dutt, Nikil, Nicolau, Alex, Earlie, Eugene

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  6. 6
    Automatic generation of operation tables for fast exploration of bypasses in embedded processors

    Automatic generation of operation tables for fast exploration of bypasses in embedded processors by Sanghyun Park, Shrivastava, A., Dutt, N., Earlie, E., Nicolau, A., Yunheung Paek

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  7. 7
    Aggregating processor free time for energy reduction

    Aggregating processor free time for energy reduction by Shrivastava, Aviral, Earlie, Eugene, Dutt, Nikil, Nicolau, Alex

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  8. 8
    Operation Tables for Scheduling in the Presence of Incomplete Bypassing

    Operation Tables for Scheduling in the Presence of Incomplete Bypassing by Shrivastava, Aviral, Earlie, Eugene, Dutt, Nikil, Nicolau, Alex

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  9. 9
    Operation tables for scheduling in the presence of incomplete bypassing

    Operation tables for scheduling in the presence of incomplete bypassing by Shrivastava, Aviral, Earlie, Eugene, Dutt, Nikil, Nicolau, Alex

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  10. 10
    Bypass aware instruction scheduling for register file power reduction

    Bypass aware instruction scheduling for register file power reduction by PARK, Sanghyun, SHRIVASTAVA, Aviral, DUTT, Nikil, NICOLAU, Alex, PAEK, Yunheung, EARLIE, Eugene

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