Search Results - Ejnioui, A.

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  1. 1
    Tiered Algorithm for Distributed Process Quiescence and Termination Detection

    Tiered Algorithm for Distributed Process Quiescence and Termination Detection by DeMara, R.F., Yili Tseng, Ejnioui, A.

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  2. 2
    Routing on field-programmable switch matrices

    Routing on field-programmable switch matrices by Ejnioui, A., Ranganathan, N.

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  3. 3
    Multiterminal net routing for partial crossbar-based multi-FPGA systems

    Multiterminal net routing for partial crossbar-based multi-FPGA systems by Ejnioui, A., Ranganathan, N.

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  4. 4
    A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems

    A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems by Ejnioui, A., Ranganathan, N.

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  5. 5
    Runtime Adaptation in Reconfigurable System-on-Chips

    Runtime Adaptation in Reconfigurable System-on-Chips by Ejnioui, A.

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  6. 6
    CAPABILITY CLASSES OF MULTIPROCESSOR SYNCHRONIZATION TECHNIQUES

    CAPABILITY CLASSES OF MULTIPROCESSOR SYNCHRONIZATION TECHNIQUES by DeMara, R.F., Tseng, Y., Drake, K., Ejnioui, A.

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  7. 7
    Capability Classes of Multiprocessor Synchronization Techniques

    Capability Classes of Multiprocessor Synchronization Techniques by DeMara, R.F., Tseng, Y., Drake, K., Ejnioui, A.

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  8. 8
    A tree-matching chip

    A tree-matching chip by Krishna, V., Ranganathan, N., Ejnioui, A.

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  9. 9
    Design and implementation of double precision floating point division and square root on FPGAs

    Design and implementation of double precision floating point division and square root on FPGAs by Thakkar, A.J., Ejnioui, A.

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  10. 10
    Control and data flow graph extraction for high-level synthesis

    Control and data flow graph extraction for high-level synthesis by Namballa, R., Ranganathan, N., Ejnioui, A.

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  11. 11
    Systolic algorithms for tree pattern matching

    Systolic algorithms for tree pattern matching by Ejnioui, A., Ranganathan, N.

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  12. 12
    A tree matching chip

    A tree matching chip by Krishna, V., Ejnioui, A., Ranganathan, N.

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  13. 13
    Pipeline design based on self-resetting stage logic

    Pipeline design based on self-resetting stage logic by Ejnioui, A., Alsharqawi, A.

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  14. 14
    A reconfigurable memory management core for Java applications

    A reconfigurable memory management core for Java applications by Ejnioui, A., Rhiati, A.

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  15. 15
    Pipeline-level control of self-resetting pipelines

    Pipeline-level control of self-resetting pipelines by Ejnioui, A., Alsharqawi, A.

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  16. 16
    A partitioning algorithm for technology-mapped designs on single-chip emulation systems

    A partitioning algorithm for technology-mapped designs on single-chip emulation systems by EJNIOUI, Abdel, RANGANATHAN, N

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  17. 17
    A VLSI architecture for object recognition using tree matching

    A VLSI architecture for object recognition using tree matching by Sitaraman, K., Ranganathan, N., Ejnioui, A.

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  18. 18
    Routing on switch matrix multi-FPGA systems

    Routing on switch matrix multi-FPGA systems by Ejnioui, A., Ranganathan, N.

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  19. 19
    Design partitioning on single-chip emulation systems

    Design partitioning on single-chip emulation systems by Ejnioui, A., Ranganathan, N.

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  20. 20
    FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline

    FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline by Ejnioui, A.

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