Search Results - Ekanayake, Virantha

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  1. 1
    Mitigation of Single-Event Charge Sharing in a Commercial FPGA Architecture

    Mitigation of Single-Event Charge Sharing in a Commercial FPGA Architecture by Kelly, Andrew T., Alles, Michael L., Ball, Dennis R., Massengill, Lloyd W., Ramaswamy, S., Haddad, Nadim F., Brown, Ronald D., Fleming, Patrick R., Chan, Ernesto, Ekanayake, Virantha, Kelly, Clinton W., Pelosi, Christopher, McMorrow, Dale, Buchner, Steven P., Warner, Jeffery H., Berg, Melanie D.

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  2. 2
    An ultra low-power processor for sensor networks

    An ultra low-power processor for sensor networks by Ekanayake, Virantha, Kelly IV, Clinton, Manohar, Rajit

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  3. 3
    An ultra low-power processor for sensor networks

    An ultra low-power processor for sensor networks by Ekanayake, Virantha, Kelly, Clinton, Manohar, Rajit

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  4. 4
    An ultra low-power processor for sensor networks

    An ultra low-power processor for sensor networks by Ekanayake, Virantha, Clinton Kelly, I V, Manohar, Rajit

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  5. 5
    BitSNAP: dynamic significance compression for a low-energy sensor network asynchronous processor

    BitSNAP: dynamic significance compression for a low-energy sensor network asynchronous processor by Ekanayake, V.N., Kelly, C., Manohar, R.

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  6. 6
    SNAP: a Sensor-Network Asynchronous Processor

    SNAP: a Sensor-Network Asynchronous Processor by Kelly, C., Ekanayake, V., Manohar, R.

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  7. 7
    A radiation hardened reconfigurable FPGA

    A radiation hardened reconfigurable FPGA by Ramaswamy, S., Rockett, L., Patel, D., Danziger, S., Manohar, R., Kelly, C.W., Holt, J.L., Ekanayake, V., Elftmann, D.

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  8. 8
    Asynchronous DRAM design and synthesis

    Asynchronous DRAM design and synthesis by Ekanayake, V.N., Manohar, R.

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  9. 9
    A biologically inspired tactile sensor array utilizing phase-based computation

    A biologically inspired tactile sensor array utilizing phase-based computation by Cassidy, A., Ekanayake, V.

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  10. 10
    Mitigation of single-event charge sharing in a commercial FPGA architecture

    Mitigation of single-event charge sharing in a commercial FPGA architecture by Kelly, Andrew T., Alles, Michael L., Ball, Dennis R., Massengill, Lloyd W., Ramaswamy, S., Haddad, Nadim F., Brown, Ronald D., Fleming, Patrick R., Chan, Ernesto, Ekanayake, Virantha, Kelly, Clinton W., Pelosi, Christopher, McMorrow, Dale, Buchner, Steven P., Warner, Jeffery H., Berg, Melanie D.

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  11. 11
    An ultra low-power processor for sensor networks

    An ultra low-power processor for sensor networks by Ekanayake, Virantha, Kelly, Clinton, Manohar, Rajit

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  12. 12
    An ultra low-power processor for sensor networks

    An ultra low-power processor for sensor networks by EKANAYAKE, Virantha, KELLY, Clinton IV, MANOHAR, Rajit

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