Search Results - El-Maleh, A.H.

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  1. 1
    Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation

    Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation by El-Maleh, A.H., Khursheed, S.S., Sait, S.M.

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  2. 2
    Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation

    Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation by El-Maleh, A.H., Khursheed, S.S., Sait, S.M.

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  3. 3
    A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decompos

    A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decompos by El-Maleh, A.H., Ali, M.I., Al-Yamani, A.A.

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  4. 4
    Extended frequency-directed run-length code with improved application to system-on-a-chip test data compression

    Extended frequency-directed run-length code with improved application to system-on-a-chip test data compression by El-Maleh, A.H., Al-Abaji, R.H.

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  5. 5
    Delay-fault testability preservation of the concurrent decomposition and factorization transformations

    Delay-fault testability preservation of the concurrent decomposition and factorization transformations by El-Maleh, A.H., Rajski, J.

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  6. 6
    Transistor-level based defect tolerance for reliable nanoelectronics

    Transistor-level based defect tolerance for reliable nanoelectronics by El-Maleh, A.H., Al-Hashimi, B.M., Melouki, A.

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  7. 7
    A hybrid test compression technique for efficient testing of systems-on-a-chip

    A hybrid test compression technique for efficient testing of systems-on-a-chip by El-Maleh, A.H.

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  8. 8
    A class-based clustering static compaction technique for combinational circuits

    A class-based clustering static compaction technique for combinational circuits by El-Maleh, A.H., Osais, Y.E.

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  9. 9
    On test vector reordering for combinational circuits

    On test vector reordering for combinational circuits by El-Maleh, A.H., Osais, Y.E.

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  10. 10
    A static test compaction technique for combinational circuits based on independent fault clustering

    A static test compaction technique for combinational circuits based on independent fault clustering by Osais, Y.E., El-Maleh, A.H.

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  11. 11
    A retiming-based test pattern generator design for built-in self test of data path architectures

    A retiming-based test pattern generator design for built-in self test of data path architectures by El-Maleh, A.H., Osais, Y.E.

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  12. 12
    Enhancing performance of iterative heuristics for VLSI netlist partitioning

    Enhancing performance of iterative heuristics for VLSI netlist partitioning by Sait, S.M., El-Maleh, A.H., Al-Abaji, R.H.

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  13. 13
    An evolutionary meta-heuristic for state justification in sequential automatic test pattern generation

    An evolutionary meta-heuristic for state justification in sequential automatic test pattern generation by El-Maleh, A.H., Sait, S.M., Shazli, S.Z.

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  14. 14
    Iterative heuristics for multiobjective VLSI standard cell placement

    Iterative heuristics for multiobjective VLSI standard cell placement by Sait, S.M., Youssef, H., El-Maleh, A.H., Minhas, M.R.

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  15. 15
    A state machine synthesizer with Weinberger arrays

    A state machine synthesizer with Weinberger arrays by El-Maleh, A.H., Sait, S.M.

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