Search Results - Emmert, John M

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  1. 1
    A Survey of Electromagnetic Radiation Based Hardware Assurance and Reliability Monitoring Methods in Integrated Circuits

    A Survey of Electromagnetic Radiation Based Hardware Assurance and Reliability Monitoring Methods in Integrated Circuits by Vutukuru, Manoj Yasaswi, Emmert, John M., Jha, Rashmi

    Published in IEEE access
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  2. 2
    Research and Development Priorities for Security of Embedded Hardware Devices

    Research and Development Priorities for Security of Embedded Hardware Devices by Moghadasi, Negin, Luu, Mai, Adekunle, Rahman O., Polmateer, Thomas L., Manasco, Mark C., Emmert, John M., Lambert, James H.

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  3. 3
    A survey of fault tolerant methodologies for FPGAs

    A survey of fault tolerant methodologies for FPGAs by Cheatham, Jason A, Emmert, John M, Baumgart, Stan

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  4. 4
    THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs

    THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs by Emmert, John M., Perumalla, Anvesh K., Hudson, Tristan J., Concha, Luis M.

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  5. 5
    An Asynchronous FPGA THx2 Programmable Cell for Mitigating Side-Channel Attacks

    An Asynchronous FPGA THx2 Programmable Cell for Mitigating Side-Channel Attacks by Emmert, John M., Perumalla, Anvesh, Concha, Luis

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  6. 6
    Area Efficient Asynchronous Circuits for Side Channel Attack Mitigation

    Area Efficient Asynchronous Circuits for Side Channel Attack Mitigation by Phillips, Dallas A., Chen, Pingxiuqi, Emmert, John M.

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  7. 7
    Fully BEOL-Compatible Switch Boxes Using RRAMs and Thin Film Transistors for Reconfigurable and Secure ICs

    Fully BEOL-Compatible Switch Boxes Using RRAMs and Thin Film Transistors for Reconfigurable and Secure ICs by Ruen, Aaron, Barua, Abhijeet, Jha, Rashmi, Emmert, John M.

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  8. 8
    Online Fault Tolerance for FPGA Logic Blocks

    Online Fault Tolerance for FPGA Logic Blocks by Emmert, J.M., Stroud, C.E., Abramovici, M.

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  9. 9
    Online BIST and BIST-based diagnosis of FPGA logic blocks

    Online BIST and BIST-based diagnosis of FPGA logic blocks by Abramovici, M., Stroud, C.E., Emmert, J.M.

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  10. 10
    Fast FPGA Reverse Engineering for Hardware Metering and Fingerprinting

    Fast FPGA Reverse Engineering for Hardware Metering and Fingerprinting by Perumalla, Anvesh, Stowasser, Heiko, Emmert, John M.

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  11. 11
    Critical Datapath Cells for NCL Asynchronous Circuit Area Reduction

    Critical Datapath Cells for NCL Asynchronous Circuit Area Reduction by Phillips, Dallas A., Emmert, John M.

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  12. 12
    An Asynchronous MPGA THx2 Cell and Architecture for Mitigating Side-Channel Attacks

    An Asynchronous MPGA THx2 Cell and Architecture for Mitigating Side-Channel Attacks by Emmert, John M., Perumalla, Anvesh

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  13. 13
    EMC: Efficient Muller C-Element Implementation for High Bit-width Asynchronous Applications

    EMC: Efficient Muller C-Element Implementation for High Bit-width Asynchronous Applications by Emmert, John M., VanDewerker, Sara A.

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  14. 14
    Determining Confidence in FPGA Bitstream Reverse Engineering Results

    Determining Confidence in FPGA Bitstream Reverse Engineering Results by Williams, Ronald D., Collier, Zachary A., Polmateer, Thomas L., Lambert, James H., Perumalla, Anvesh, Emmert, John M.

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  15. 15
    NSF CHEST IUCRC: Case Study for Leveraging NSF IUCRCs for R&D

    NSF CHEST IUCRC: Case Study for Leveraging NSF IUCRCs for R&D by Emmert, John M., Perumalla, Anvesh, Fischer, Scott, Vincent, Barry

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  16. 16
    On Using Tabu Search for Design Automation of VLSI Systems

    On Using Tabu Search for Design Automation of VLSI Systems by Emmert, John M, Lodha, Sandeep, Bhatia, Dinesh K

    Published in Journal of heuristics
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  17. 17
    A Fault Tolerant Technique for FPGAs

    A Fault Tolerant Technique for FPGAs by Emmert, John M, Bhatia, Dinesh K

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  18. 18
    Two-dimensional Placement Using Tabu Search

    Two-dimensional Placement Using Tabu Search by Emmert, John M., Bhatia, Dinesh K.

    Published in VLSI Design
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  19. 19
    A New Method for Testing Re-Programmable PLAs

    A New Method for Testing Re-Programmable PLAs by Stroud, Charles E, Bailey, James R, Emmert, Johan R

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  20. 20
    Gotcha! I Know What You are Doing on the FPGA Cloud: Fingerprinting Co-Located Cloud FPGA Accelerators via Measuring Communication Links

    Gotcha! I Know What You are Doing on the FPGA Cloud: Fingerprinting Co-Located Cloud FPGA Accelerators via Measuring Communication Links by Fang, Chongzhou, Miao, Ning, Wang, Han, Zhou, Jiacheng, Sheaves, Tyler, Emmert, John M, Avesta Sasan, Homayoun, Houman

    Published in arXiv.org
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