Search Results - Epassa, H.G.

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  1. 1
    Implementation of a cycle by cycle variable speed processor

    Implementation of a cycle by cycle variable speed processor by Epassa, H.G., Boyer, F.R., Savaria, Y.

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    A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications

    A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications by Boyer, F.-R., Epassa, H.G., Pontikakis, B., Savaria, Y., Wei Ling

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