A Neural Network Prefetcher for Arbitrary Memory Access Patterns by Peled, Leeor, Weiser, Uri, Etsion, Yoav

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Single-graph multiple flows: Energy efficient design alternative for GPGPUs by Voitsechov, Dani, Etsion, Yoav

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Hybrid Dataflow/von-Neumann Architectures by Yazdanpanah, Fahimeh, Alvarez-Martinez, Carlos, Jimenez-Gonzalez, Daniel, Etsion, Yoav

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Semantic locality and context-based prefetching using reinforcement learning by Peled, Leeor, Mannor, Shie, Weiser, Uri, Etsion, Yoav

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Backfilling Using System-Generated Predictions Rather than User Runtime Estimates by Tsafrir, D., Etsion, Y., Feitelson, D.G.

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Do-It-Yourself Virtual Memory Translation by Alam, Hanna, Zhang, Tianhao, Erez, Mattan, Etsion, Yoav

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Exploration of Knowledge Graphs via Online Aggregation by Kalinsky, Oren, Hogan, Aidan, Mishali, Oren, Etsion, Yoav, Kimelfeld, Benny

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L1 Cache Filtering Through Random Selection of Memory References by Etsion, Y., Feitelson, D.G.

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Using SMT to Accelerate Nested Virtualization by Vilanova, Lluis, Amit, Nadav, Etsion, Yoav

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Probabilistic Prediction of Temporal Locality by Etsion, Y., Feitelson, D.G.

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Exploiting Core Working Sets to Filter the L1 Cache with Random Sampling by Etsion, Y., Feitelson, D. G.

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CODOMs: Protecting software with Code-centric memory Domains by Vilanova, Lluis, Ben-Yehuda, Muli, Navarro, Nacho, Etsion, Yoav, Valero, Mateo

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Loop-Aware Memory Prefetching Using Code Block Working Sets by Fuchs, Adi, Mannor, Shie, Weiser, Uri, Etsion, Yoav

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On the simulation of large-scale architectures using multiple application abstraction levels by Rico, Alejandro, Cabarcas, Felipe, Villavieja, Carlos, Pavlovic, Milan, Vega, Augusto, Etsion, Yoav, Ramirez, Alex, Valero, Mateo

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Task Superscalar: An Out-of-Order Task Pipeline by Etsion, Y, Cabarcas, F, Rico, A, Ramirez, A, Badia, R M, Ayguade, E, Labarta, J, Valero, M

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DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory by Villavieja, C., Karakostas, V., Vilanova, L., Etsion, Y., Ramirez, A., Mendelson, A., Navarro, N., Cristal, A., Unsal, O. S.

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DFiant: A dataflow hardware description language by Port, Oron, Etsion, Yoav

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Memristor-Based Multithreading by Kvatinsky, Shahar, Nacson, Yuval H., Etsion, Yoav, Friedman, Eby G., Kolodny, Avinoam, Weiser, Uri C.

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Analysis of the Task Superscalar Architecture Hardware Design by Yazdanpanah, Fahimeh, Jimenez-Gonzalez, Daniel, Alvarez-Martinez, Carlos, Etsion, Yoav, Badia, Rosa M.

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Process prioritization using output production: Scheduling for multimedia by Etsion, Yoav, Tsafrir, Dan, Feitelson, Dror G.

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