Advanced SOI CMOS transistor technology for high performance microprocessors by Horstmann, M., Wiatr, M., Wei, A., Hoentschel, J., Feudel, Th, Scheiper, Th, Stephan, R., Gerhadt, M., Krügel, S., Raab, M.

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A technology oriented model for transient diffusion and activation of boron in silicon by Höfler, A., Feudel, Th, Strecker, N., Fichtner, W., Stegemann, K.-H., Syhre, H., Dallmann, G.

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Advanced SOI CMOS transistor technology for high performance microprocessors: Papers Selected from the Ultimate Integration on Silicon Conference 2009, ULIS 2009 by HORSTMANN, M, WIATR, M, WEI, A, HOENTSCHEL, J, FEUDEL, Th, SCHEIPER, Th, STEPHAN, R, GERHADT, M, KRÜGEL, S, RAAB, M

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Novel approaches to improve laser annealed SOI-MOSFETs by Herrmann, T., Feudel, Th, Horstmann, M., Hoentschel, J., Herrmann, L., Herden, M., Klix, W., Stenzel, R.

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Reduced Parameter Fluctuation with Laser and Flash Lamp Anneal for 65nm Volume Production by Feudel, Thomas, Bayha, B, Burbach, G, Gerhardt, M, Herrmann, L, Herden, M, Mantei, T, Ehrichs, E, Greenlaw, M, Horstmann, Manfred

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Sub-50 nm gate length SOI transistor development for high performance microprocessors by Horstmann, M., Greenlaw, D., Feudel, Th, Wei, A., Frohberg, K., Burbach, G., Gerhardt, M., Lenski, M., Stephan, R., Wieczorek, K., Schaller, M., Hohage, J., Ruelke, H., Klais, J., Huebler, P., Luning, S., Bentum, R. van, Grasshoff, G., Schwan, C., Cheek, J., Buller, J., Krishnan, S., Raab, M., Kepler, N.

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Temperature scaling for 35 nm gate length high-performance CMOS by Feudel, Th, Horstmann, M., Gerhardt, M., Herden, M., Herrmann, L., Gehre, D., Krueger, Ch, Greenlaw, D., Raab, M.

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Temperature scaling for 35nm gate length high-performance CMOS by Feudel, Th, Horstmann, M., Gerhardt, M., Herden, M., Herrmann, L., Gehre, D., Krueger, Ch, Greenlaw, D., Raab, M.

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Sub-50nm gate length SOI transistor development for high performance microprocessors by Horstmann, M., Greenlaw, D., Feudel, Th, Wei, A., Frohberg, K., Burbach, G., Gerhardt, M., Lenski, M., Stephan, R., Wieczorek, K., Schaller, M., Hohage, J., Ruelke, H., Klais, J., Huebler, P., Luning, S., Bentum, R. van, Grasshoff, G., Schwan, C., Cheek, J., Buller, J., Krishnan, S., Raab, M., Kepler, N.

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Process Integration Issues with Spike, Flash and Laser Anneal Implementation for 90 and 65 NM Technologies by Feudel, Th, Horstmann, M., Herrmann, L., Herden, M., Gerhardt, M., Greenlaw, D., Fisher, P., Kluth, J.

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Advanced SOI CMOS transistor technology for high performance microprocessors by Horstmann, M., Wiatr, M., Wei, A., Hoentschel, J., Feudel, T., Scheiper, T., Stephan, R., Gerhadt, M., Raab, M.

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Review on Process-Induced Strain Techniques for Advanced Logic Technologies by Wiatr, M., Feudel, T., Wei, A., Mowry, A., Boschke, R., Javorka, P., Gehring, A., Kammler, T., Lenski, M., Frohberg, K., Richter, R., Horstmann, M., Greenlaw, D.

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Advanced transistor structures for high performance microprocessors by Horstmann, M., Greenlaw, D., Feudel, T., Wei, A., Frohberg, K., Burbach, G., Gerhardt, M., Lenski, M., Stephan, R., Wieczorek, K., Schaller, M., Hohage, J., Ruelke, H., Klais, J., Huebler, P., Luning, S., van Bentum, R., Grasshoff, G., Schwan, C., Cheek, J., Buller, J., Krishnan, S., Raab, M., Kepler, N.

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High performance SOI technology for sub-45nm gate length CMOS manufacturing by HORSTMANN, M, GREENLAW, D, SCHWAN, C, PETERS, C, LENSKI, M, PRESS, P, KAMMLER, Th, BIERSTEDT, H, OTTERBACH, R, NEU, A, WIECZOREK, K, SCHALLER, M, HUEBLER, P, SALZ, H, HOHAGE, J, RUELKE, H, KLAIS, J, GRASSHOFF, G, EHRICHS, E, GOAD, S, RAAB, M, KEPLER, N, STEPHAN, R, FEUDEL, Th, WEI, A, FROHBERG, K, HOENTSCHEL, J, JAVORKA, P, BURBACH, G

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Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing by Yang, H.S., Malik, R., Narasimha, S., Li, Y., Divakaruni, R., Agnello, P., Allen, S., Antreasyan, A., Arnold, J.C., Bandy, K., Belyansky, M., Bonnoit, A., Bronner, G., Chan, V., Chen, X., Chen, Z., Chidambarrao, D., Chou, A., Clark, W., Crowder, S.W., Engel, B., Harifuchi, H., Huang, S.F., Jagannathan, R., Jamin, F.F., Kohyama, Y., Kuroda, H., Lai, C.W., Lee, H.K., Lee, W.-H., Lim, E.H., Lai, W., Mallikarjunan, A., Matsumoto, K., McKnight, A., Nayak, J., Ng, H.Y., Panda, S., Rengarajan, R., Steigerwalt, M., Subbanna, S., Subramanian, K., Sudijono, J., Sudo, G., Sun, S.-P., Tessier, B., Toyoshima, Y., Tran, P., Wise, R., Wong, R., Yang, I.Y., Wann, C.H., Su, L.T., Horstmann, M., Feudel, Th, Wei, A., Frohberg, K., Burbach, G., Gerhardt, M., Lenski, M., Stephan, R., Wieczorek, K., Schaller, M., Salz, H., Hohage, J., Ruelke, H., Klais, J., Huebler, P., Luning, S., van Bentum, R., Grasshoff, G., Schwan, C., Ehrichs, E., Goad, S., Buller, J., Krishnan, S., Greenlaw, D., Raab, M., Kepler, N.

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Solid-phase epitaxial regrowth of a shallow amorphised Si layer studied by X-ray and medium energy ion scattering by Capello, L., Metzger, T.H., Werner, M., van den Berg, J.A., Servidori, M., Herden, M., Feudel, T.

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Simulation of range profiles for boron implantation into SiO2/Si and Si3N4/SiO2/Si targets by Posselt, M., Feudel, T., Th ter, G.

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