A Resonant Global Clock Distribution for the Cell Broadband Engine Processor by Chan, S.C., Restle, P.J., Bucelot, T.J., Liberty, J.S., Weitzel, S., Keaty, J.M., Flachs, B., Volant, R., Kapusta, P., Zimmerman, J.S.

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Synergistic Processing in Cell's Multicore Architecture by Gschwind, Michael, Hofstee, H. Peter, Flachs, Brian, Hopkins, Martin, Watanabe, Yukio, Yamazaki, Takeshi

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A Resonant Global Clock Distribution for the Cell Broadband-Engine Processor by Chan, Steven, Restle, Phillip, Bucelot, Thomas, Weitzel, Stephen, Keaty, John, Liberty, John, Flachs, Brian, Volant, Richard, Kapusta, Peter, Zimmerman, Jeff

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The microarchitecture of the synergistic processor for a cell processor by Flachs, B., Asano, S., Dhong, S.H., Hofstee, H.P., Gervais, G., Roy Kim, Le, T., Peichun Liu, Leenstra, J., Liberty, J., Michael, B., Hwa-Joon Oh, Mueller, S.M., Takahashi, O., Hatakeyama, A., Watanabe, Y., Yano, N., Brokenshire, D.A., Peyravian, M., Vandung To, Iwata, E.

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The Hector distributed run-time environment by Russ, S.H., Robinson, J., Flachs, B.K., Heckel, B.

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4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance by Mair, Hugh T., Gammie, Gordon, Wang, Alice, Lagerquist, Rolf, Chung, C. J., Gururajarao, Sumanth, Kao, Ping, Rajagopalan, Anand, Saha, Anirban, Jain, Amit, Wang, Ericbill, Ouyang, Shichin, Huajun Wen, Thippana, Achuta, HsinChen Chen, Rahman, Syed, Chau, Minh, Varma, Anshul, Flachs, Brian, Peng, Mark, Tsai, Alfred, Lin, Vincent, Ue Fu, Wuan Kuo, Lee-Kee Yong, Clavin Peng, Leo Shieh, Jengding Wu, Uming Ko

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Power-conscious design of the Cell processor's synergistic processor element by Takahashi, O., Cottier, S., Dhong, S.H., Flachs, B., Silberman, J.

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Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI by Flachs, B., Asano, S., Dhong, S. H., Hofstee, H. P., Gervais, G., Kim, R., Le, T., Liu, P., Leenstra, J., Liberty, J. S., Michael, B., Oh, H.-J., Mueller, S. M., Takahashi, O., Hirairi, K., Kawasumi, A., Murakami, H., Noro, H., Onishi, S., Pille, J., Silberman, J., Yong, S., Hatakeyama, A., Watanabe, Y., Yano, N., Brokenshire, D. A., Peyravian, M., To, V., Iwata, E.

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A task migration implementation of the Message-Passing Interface by Robinson, J., Russ, S.H., Flachs, B., Heckel, B.

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Distributed On-chip Power Supply Noise Characterization of the Cell Broadband Engine by Zhou, Yaping, Harvey, Paul M., Flachs, Brian, Liberty, John, Gervais, Gilles, Mandrekar, Rohan, Chen, Howard H., Tamura, Tetsuji

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A method to measure impedance of chip/package/board power supply system using pseudo-impulse current by Zhou, Y., Dhong, S.H., Flachs, B., Harvey, P.M., Michael, B.W.

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The Power Conscious Synergistic Processor Element of a Cell Processor by Takahashi, O., Cottier, S., Dhong, S.H., Flachs, B., Hirairi, K., Peter Hofstee, H., Michael, B., Noro, H., Wendel, D., White, M.

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