Analysis of resistive defects on a foundry 8T SRAM-based IMC architecture by Ammoura, L., Flottes, M.-L., Girard, P., Noel, J.-P., Virazel, A.

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Assessing body built-in current sensors for detection of multiple transient faults by Viera, R.A.C., Dutertre, J.-M., Flottes, M.-L., Potin, O., Natale, G. Di, Rouzeyre, B., Bastos, R. Possamai

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Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection by Dutertre, J.M., Possamai Bastos, R., Potin, O., Flottes, M.L., Rouzeyre, B., Di Natale, G.

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Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS by Dutertre, J.M., Possamai Bastos, R., Potin, O., Flottes, M.L., Rouzeyre, B., Di Natale, G., Sarafianos, A.

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Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture by Ammoura, L., Flottes, M.-L., Girard, P., Noel, J.-P., Virazel, A.

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A Lightweight, Plug-and-Play and Autonomous JTAG Authentication IP for Secure Device Testing by Lapeyre, S., Valette, N., Merandat, M., Flottes, M.-L., Rouzeyre, B., Virazel, A.

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A Plug and Play Digital ABIST Controller for Analog Sensors in Secure Devices by Lapeyre, S., Valette, N., Merandat, M., Flottes, M.-L., Rouzeyre, B., Virazel, A.

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Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs by Azais, F., Bernard, S., Comte, M., Deveautour, B., Dupuis, S., Badawi, H. El, Flottes, M.-L., Girard, P., Kerzerho, V., Latorre, L., Lefevre, F., Rouzeyre, B., Valea, E., Vayssadel, T., Virazel, A.

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A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard by Di Natale, G., Doulcier, M., Flottes, M. L., Rouzeyre, B.

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Figure of Merits of 28nm Si Technologies for Implementing Laser Attack Resistant Security Dedicated Circuits by de Castro, S., Di Natale, G., Flottes, M.-L., Rouzeyre, B., Dutertre, J.-M.

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A bulk built-in sensor for detection of fault attacks by Possamai Bastos, R., Sill Torres, F., Dutertre, J-M, Flottes, M-L, Di Natale, G., Rouzeyre, B.

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Mutation Sampling Technique for the Generation of Structural Test Data by Scholive, M., Beroulle, V., Robach, C., Flottes, M. L., Rouzeyre, B.

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A Unified DFT Approach for BIST and External Test by Flottes, M-l, Landrault, C, Petitqueux, A

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Laser-induced fault effects in security-dedicated circuits by Leveugle, R., Maistri, P., Vanhauwaert, P., Lu, F., Di Natale, G., Flottes, M.-L, Rouzeyre, B., Papadimitriou, A., Hely, D., Beroulle, V., Hubert, G., De Castro, S., Dutertre, J.-M, Sarafianos, A., Boher, N., Lisart, M., Damiens, J., Candelier, P., Tavernier, C.

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A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults by Possamai Bastos, R., Sill Torres, F., Dutertre, J.-M, Flottes, M.-L, Di Natale, G., Rouzeyre, B.

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Design for sequential testability: an internal state reseeding approach for 100 % fault coverage by Flottes, M.L., Landrault, C., Petitqueux, A.

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Scan design and secure chip [secure IC testing] by Hely, D., Flottes, M.-L., Bancel, F., Rouzeyre, B., Berard, N., Renovell, M.

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A simple and effective compression scheme for test pins reduction by Flottes, M.-L., Poirier, R., Rouzeyre, B.

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Self-Test Techniques for Crypto-Devices by Di Natale, G., Doulcier, M., Flottes, M.-L., Rouzeyre, B.

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A heuristic for test scheduling at system level by Flottes, M.-L., Pouget, J., Rouzeyre, B.

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