An MMCM-based high-speed true random number generator for Xilinx FPGA by Fujieda, Naoki, Takashima, Sogo

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On the Feasibility of TERO-Based True Random Number Generator on Xilinx FPGAs by Fujieda, Naoki

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An XOR-based parameterization for instruction register files by Fujieda, Naoki, Ichikawa, Shuichi

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Attenuation Model for Error Correction of Ultrasonic Positioning System by Fujieda, Naoki, Shinohara, Takumi, Ichikawa, Shuichi, Sakaguchi, Yuhki, Matsuoka, Shunsuke, Kawaguchi, Hideki

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A Virtual Cache for Overlapped Memory Accesses of Path ORAM by Fujieda, Naoki, Yamauchi, Ryo, Fujita, Hiroki, Ichikawa, Shuichi

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An Analysis of DCM-Based True Random Number Generator by Fujieda, Naoki, Takeda, Masaaki, Ichikawa, Shuichi

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A true random number generator that utilizes thermal noise in a programmable system‐on‐chip (PSoC) by Matsuoka, Shunsuke, Ichikawa, Shuichi, Fujieda, Naoki

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An HLS implementation of on-the-fly randomness test for TRNGs by Oya, Ryusei, Fujieda, Naoki, Ichikawa, Shuichi

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Evaluation of Hardware Obfuscation Techniques using Obfuscation Tool oLLVM by Matsuoka, Yuumi, Fujieda, Naoki, Ichikawa, Shuichi

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Performance Evaluation of Parallel SAT Solver on Xeon Phi Processor by Nishiwaki, Shintaro, Fujieda, Naoki, Ichikawa, Shuichi

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Evaluation of Special Instruction Implementations in Soft Processors for High-level Synthesis by Iwahara, Kazuki, Ichikawa, Shuichi, Fujieda, Naoki, 和輝, 岩原, 周一, 市川, 直輝, 藤枝

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Design and implementation of instruction indirection for embedded software obfuscation by Fujieda, Naoki, Tanaka, Tasuku, Ichikawa, Shuichi

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Research on Fault Tolerant Processor using Dynamic Reconfiguration by Ogido, Seiya, Yamada, Chikatoshi, Miyagi, Kei, Ichikawa, Shuichi, Fujieda, Naoki

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Improved Parameter Estimation Method for Bilateral Filter with Distribution Distance by Makishi, Taiki, Ichikawa, Shuichi, Fujieda, Naoki, Yamada, Chikatoshi, Miyagi, Kei

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A light-weight implementation of latch-based true random number generator by Fujieda, Naoki, Kishibe, Hitomi, Ichikawa, Shuichi

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Random Number Generation from Internal LFSR and Fluctuation of Sampling Interval by Masaoka, Hidetaka, Ichikawa, Shuichi, Fujieda, Naoki, 秀崇, 正岡, 周一, 市川, 直輝, 藤枝

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An Obfuscated Hardwired Sequence Control System Generated by High Level Synthesis by Ishigaki, Yoshiki, Fujieda, Naoki, Matsuoka, Yuumi, Uyama, Kazuki, Ichikawa, Shuichi

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Experimental Implementation of Fault Tolerance Using Dynamic Partial Reconfiguration on Xilinx Zynq-7000 SoC by Ogido, Seiya, Ichikawa, Shuichi, Fujieda, Naoki, Yamada, Chikatoshi, Miyagi, Kei, 盛也, 荻堂, 周一, 市川, 直輝, 藤枝, 親稔, 山田, 宮城 桂

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Last Path Caching: A Simple Way to Remove Redundant Memory Accesses of Path ORAM by Fujieda, Naoki, Yamauchi, Ryo, Ichikawa, Shuichi

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An XOR-Based Approach to Merging Entries for Instruction Register Files by Fujieda, Naoki, Ichikawa, Shuichi

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