Dielectric pockets-a new concept of the junctions for deca-nanometric CMOS devices by Jurczak, M., Skotnicki, T., Gwoziecki, R., Paoli, M., Tormen, B., Ribot, P., Dutartre, D., Monfray, S., Galvier, J.

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Plasma doping for shallow junctions by Goeckner, M. J., Felch, S. B., Fang, Z., Lenoble, D., Galvier, J., Grouillet, A., Yeap, G. C.-F., Bang, D., Lin, M.-R.

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Front-end, single-wafer diffusion processing for advanced 300-mm fabrication lines by Bensahel, D, Vandelle, B, Morin, C, Martins, J, Galvier, J, Vialletelle, P, Henry, M

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Dielectric pockets - A new concept of the junction for deca-nanometric CMOS devices by Jurczak, M, Skotnicki, T, Gwoziecki, R, Paoli, M, Tormen, B, Ribot, P, Dutartre, D, Monfray, S, Galvier, J

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Well-controlled, selectively under-etched Si/SiGe gates for RF and high performance CMOS by Skotnicki, T., Ricci, G., Galvier, J., Jurczak, M., Martins, J., Paoli, M., Tormen, B., Pantel, R., Hernandez, C., Campidelli, I., Josse, E.

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1.62\mu \mathrm Global Shutter Quantum Dot Image Sensor Optimized for Near and Shortwave Infrared by Steckel, J. S., Josse, E., Pattantyus-Abraham, A. G., Bidaud, M., Mortini, B., Bilgen, H., Arnaud, O., Allegret-Maret, S., Saguin, F., Mazet, L., Lhostis, S., Berger, T., Haxaire, K., Chapelon, L. L., Parmigiani, L., Gouraud, P., Brihoum, M., Bar, P., Guillermet, M., Favreau, S., Duru, R., Fantuz, J., Ricq, S., Ney, D., Hammad, I., Roy, D., Arnaud, A., Vianne, B., Nayak, G., Virollet, N., Farys, V., Malinge, P., Tournier, A., Lalanne, F., Crocherie, A., Galvier, J., Rabary, S., Noblanc, O., Wehbe-Alause, H., Acharya, S., Singh, A., Meitzner, J., Aher, D., Yang, H., Romero, J., Chen, B., Hsu, C., Cheng, K. C., Chang, Y., Sarmiento, M., Grange, C., Mazaleyrat, E., Rochereau, K.

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First Look at Across-chip Performance Variation Using Non-Contact, Performance-Based Metrology by Babazadeh, M., Estabil, J., Borot, B., Johnson, G., Pakdaman, N., Doedel, W., Vickers, J., Steinbrueck, G., Galvier, J.

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Rounded edge mesa for submicron SOI CMOS process by Le Neel, O., Bruni, M.D, Galvier, J., Haond, M.

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Dielectric pockets - a new concept of the junctions for deca-nanometric CMOS devices by Jurczak, M., Skotnicki, T., Monfray, S., Gwoziecki, R., Paoli, M., Tormen, B., Ribot, P., Dutartre, D., Galvier, J.

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Evaluation of plasma doping for sub-0.18 /spl mu/m devices by Lenoble, D., Goeckner, M.J., Felch, S.B., Fang, Z., Galvier, J., Grouillet, A.

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Investigations of Dual Ge Gate Integration in Advanced CMOS Process by Alieu, J., Jurczak, M., Skotnicki, T., Bremond, G., Souifi, K., Paoli, M., Bensahel, D., Galvier, J., Haond, M.

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SON (silicon on nothing)-a new device architecture for the ULSI era by Jurczak, M., Skotnicki, T., Paoli, M., Tormen, B., Regolini, J.-L., Morin, C., Schiltz, A., Martins, J., Pantel, R., Galvier, J.

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Heavily doped and extremely shallow junctions on insulator by SONCTION (SilicON Cut-off juncTION) process by Skotnicki, T., Jrczak, M., Gwoziecki, R., Lenoble, D., Ribot, P., Paoli, M., Martins, J., Tormen, B., Grouillet, A., Pantel, R., Galvier, J.

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Pure Ge mid-gap gate within an industrial high performance and low standby current 0.18 /spl mu/m CMOS process by Alieu, J., Gwoziecki, R., Paoli, M., Skotnicki, T., Hernandez, C., Martin, F., Mourrain, C., Bensahel, D., Basso, M.-T., Galvier, J., Haond, M.

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