Search Results - Gangwal, O.P

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  1. 1
    An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration

    An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration by Radulescu, A., Dielissen, J., Pestana, S.G., Gangwal, O.P., Rijpkema, E., Wielage, P., Goossens, K.

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  2. 2
    A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification

    A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification by Goossens, Kees, Dielissen, John, Gangwal, Om Prakash, Pestana, Santiago Gonzalez, Radulescu, Andrei, Rijpkema, Edwin

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  3. 3
    Real-time implementation of depth map post-processing for 3D-TV in dedicated hardware

    Real-time implementation of depth map post-processing for 3D-TV in dedicated hardware by Gangwal, O.P., Djapic, B.

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  4. 4
    Depth map post-processing for 3D-TV

    Depth map post-processing for 3D-TV by Gangwal, O.P., Berretty, R.-P.

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  5. 5
    Cost-performance trade-offs in networks on chip: a simulation-based approach

    Cost-performance trade-offs in networks on chip: a simulation-based approach by Pestana, S.G., Rijpkema, E., Radulescu, A., Goossens, K., Gangwal, O.P.

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  6. 6
    Real-time implementation of depth map post-processing for 3D-TV on a programmable DSP (TriMedia)

    Real-time implementation of depth map post-processing for 3D-TV on a programmable DSP (TriMedia) by Gangwal, O.P., Coezijn, E., Berretty, R.-P.

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  7. 7
    A heterogeneous multiprocessor architecture for flexible media processing

    A heterogeneous multiprocessor architecture for flexible media processing by Rutten, M.J., van Eijndhoven, J.T.J., Jaspers, E.G.T., van der Wolf, P., Gangwal, O.P., Timmer, A., Pol, E.-J.D.

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  8. 8
    An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration

    An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration by Radulescu, A, Dielissen, J, Pestana, S.G, Gangwal, O.P, Rijpkema, E, Wielage, P, Goossens, K

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  9. 9
    Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks

    Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks by Krishnan, R., Gangwal, O.P., van Eijndhoven, J., Kumar, A.

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  10. 10
    A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems

    A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems by Gangwal, Om Prakash, Nieuwland, André, Lippens, Paul

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  11. 11
    Application design trajectory towards reusable coprocessors - MPEG case study

    Application design trajectory towards reusable coprocessors - MPEG case study by Rutten, M., Gangwal, O.P., van Eijndhoven, J., Jaspers, E., Pol, E.-J.

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  12. 12
    Eclipse: heterogeneous multiprocessor architecture for flexible media processing

    Eclipse: heterogeneous multiprocessor architecture for flexible media processing by Rutten, M.J., van Eijndhoven, J.T.J., Pol Egbert, E.D., Jaspers, G.T., van der Wolf, P., Gangwal, O.P., Timmer, A.

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  13. 13
    On automatic analysis of geometrically proximate nets in VLSI layout

    On automatic analysis of geometrically proximate nets in VLSI layout by Koranne, S., Gangwai, O.P.

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