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3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration
by
Greenhill, David
,
Ho, Ron
,
Lewis, David
,
Schmit, Herman
,
Kok Hong Chan
,
Tong, Andy
,
Atsatt, Sean
,
How, Dana
,
McElheny, Peter
,
Duwel, Keith
,
Schulz, Jeffrey
,
Faulkner, Darren
,
Iyer, Gopal
,
Chen, George
,
Hee Kong Phoon
,
Han Wooi Lim
,
Wei-Yee Koay
,
Garibay, Ty
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Custom design in a low-power/high-performance ASIC world
by
Garibay, T.
,
Reis, R.
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Custom is from Venus and synthesis from Mars
by
Puri, Ruchir
,
Joyner, William H
,
Borkar, Shekhar
,
Garibay, Ty
,
Lotz, Jonathan
,
Montoye, Robert
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6x86: the Cyrix solution to executing x86 binaries on a high performance microprocessor
by
McMahan, Steve C
,
Bluhm, Mark
,
Garibay, Raul A
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Proceedings of the IEEE
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Impact of interconnect technology scaling on SOC design methodologies
by
Nagaraj, N.S.
,
Hunter, W.R.
,
Chidambaram, P.R.
,
Garibay, T.Y.
,
Narasimha, U.
,
Hill, A.
,
Shichijo, H.
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