Search Results - Garverick, Tim L.

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    A back-biased 0.65 μm Leffn CMOS EEPROM technology for next-generation sub 7 ns programmable logic devices

    A back-biased 0.65 μm Leffn CMOS EEPROM technology for next-generation sub 7 ns programmable logic devices by Hart, Michael J., Cacharelis, Philip J., Carpenter, Roger D., Tsuei, David G., Madurawe, Raminda U., Sandhu, Bal S., Smolen, Richard G., Dumlao, Andrew P., Garverick, Tim L., McFarlane, Thomas, Manley, Martin H.

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  2. 2
    A Back - Biased 0.65 μm Leffn CMOS EEPROM Technology For Next - Generation Sub 7 ns Programmable Logic Devices

    A Back - Biased 0.65 μm Leffn CMOS EEPROM Technology For Next - Generation Sub 7 ns Programmable Logic Devices by Hart, Michael J., Cacharelis, Philip J., Carpenter, Roger D., Tsuei, David G., Madurawe, Raminda U., Sandhu, Bal S., Smolen, Richard G., Dumlao, Andrew P., Garverick, Tim L., McFarlane, Thomas, Manley, Martin H.

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