Search Results - Garyfallou, Dimitrios

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  1. 1
    Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance

    Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance by Garyfallou, Dimitrios, Simoglou, Stavros, Sketopoulos, Nikolaos, Antoniadis, Charalampos, Sotiriou, Christos P., Evmorfopoulos, Nestor, Stamoulis, George

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  2. 2
    EVT-based worst case delay estimation under process variation

    EVT-based worst case delay estimation under process variation by Antoniadis, Charalampos, Garyfallou, Dimitrios, Evmorfopoulos, Nestor, Stamoulis, Georgios

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  3. 3
    Low-rank balanced truncation of RLCk models via frequency-aware rational Krylov-based projection

    Low-rank balanced truncation of RLCk models via frequency-aware rational Krylov-based projection by Giamouzis, Christos, Garyfallou, Dimitrios, Stamoulis, George, Evmorfopoulos, Nestor

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  4. 4
    A learning-based method for performance optimization of timing analysis

    A learning-based method for performance optimization of timing analysis by Vagenas, Anastasis, Garyfallou, Dimitrios, Evmorfopoulos, Nestor, Stamoulis, George

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  5. 5
    A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees using Matrix Exponential

    A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees using Matrix Exponential by Stoikos, Pavlos, Floros, George, Garyfallou, Dimitrios, Evmorfopoulos, Nestor, Stamoulis, George

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  6. 6
    Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models

    Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models by Chatzigeorgiou, Chrysostomos, Garyfallou, Dimitrios, Floros, George, Evmorfopoulos, Nestor, Stamoulis, George

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  7. 7
    A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees using Matrix Exponential

    A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees using Matrix Exponential by Stoikos, Pavlos, Floros, George, Garyfallou, Dimitrios, Evmorfonoulos, Nestor, Stamoulis, George

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  8. 8
    A low-rank balanced truncation approach for large-scale RLCk model order reduction based on extended Krylov subspace and a frequency-aware convergence criterion

    A low-rank balanced truncation approach for large-scale RLCk model order reduction based on extended Krylov subspace and a frequency-aware convergence criterion by Giamouzis, Christos, Garyfallou, Dimitrios, Evmorfopoulos, Nestor, Stamoulis, George

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  9. 9
    Reduction of large-scale RLCk models via low-rank balanced truncation

    Reduction of large-scale RLCk models via low-rank balanced truncation by Giamouzis, Christos, Garyfallou, Dimitrios, Vagenas, Anastasis, Evmorfopoulos, Nestor

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  10. 10
    The Extended and Asymmetric Extended Krylov Subspace in Moment-Matching-Based Order Reduction of Large Circuit Models

    The Extended and Asymmetric Extended Krylov Subspace in Moment-Matching-Based Order Reduction of Large Circuit Models by Stoikos, Pavlos, Garyfallou, Dimitrios, Floros, George, Evmorfopoulos, Nestor, Stamoulis, George

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  11. 11
    Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models

    Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models by Chatzigeorgiou, Chrysostomos, Garyfallou, Dimitrios, Floros, George, Evmorfopoulos, Nestor, Stamoulis, George

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  12. 12
    MORCIC: Model Order Reduction Techniques for Electromagnetic Models of Integrated Circuits

    MORCIC: Model Order Reduction Techniques for Electromagnetic Models of Integrated Circuits by Garyfallou, Dimitrios, Stefanou, Athanasios, Giamouzis, Christos, Antoniadis, Moschos, Chararas, Georgios, Chatzis, Konstantinos, Samaras, Dimitris, Themeli, Rafaela, Michailidis, Anastasios, Gogolou, Vasiliki, Zachos, Nikos, Evmorfopoulos, Nestor, Noulis, Thomas, Pavlidis, Vasilis F, Hatzopoulos, Alkiviadis, Chatzineofytou, Elpida, Moisiadis, Yiannis

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  13. 13
    A Gate-Level SER Estimation Tool With Event-Driven Dynamic Timing and SET Height Consideration

    A Gate-Level SER Estimation Tool With Event-Driven Dynamic Timing and SET Height Consideration by Paliaroutis, Georgios-Ioannis, Tsoumanis, Pelopidas, Garyfallou, Dimitrios, Vagenas, Anastasis, Evmorfopoulos, Nestor, Stamoulis, George

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