Implementation of binarized neural networks immune to device variation and voltage drop employing resistive random access memory bridges and capacitive neurons by Ezzadeen, Mona, Majumdar, Atreya, Valorge, Olivier, Castellani, Niccolo, Gherman, Valentin, Regis, Guillaume, Giraud, Bastien, Noel, Jean-Philippe, Meli, Valentina, Bocquet, Marc, Andrieu, Francois, Querlioz, Damien, Portal, Jean-Michel

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Sequential Decoders for Binary Linear Block ECCs by Gherman, Valentin, Laffond, Cyrille

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Error correction improvement based on weak-bit-flipping for resistive memories by Gherman, Valentin, Ciampolini, Lorenzo, Evain, Samuel, Ricavy, Sébastien

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Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro by Giraud, Bastien, Ricavy, Sebastien, Laffond, Cyrille, Sever, Ilan, Gherman, Valentin, Lepin, Florent, Diallo, Mariam, Zenati, Khadija, Dumas, Sylvain, Guille, Olivier, Vershkov, Maxim, Bricalli, Alessandro, Piccolboni, Giuseppe, Noel, Jean-Philippe, Samir, Anass, Pillonnet, Gael, Thonnart, Yvain, Molas, Gabriel

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Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities by Gherman, Valentin, Evain, Samuel, Giraud, Bastien

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Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with selective refresh by Farjallah, Emna, Armani, Jean-Marc, Gherman, Valentin, Dilillo, Luigi

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On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits by Deveautour, B., Virazel, A., Girard, P., Gherman, V.

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Error Correction Schemes with Erasure Information for Fast Memories by Evain, Samuel, Savin, Valentin, Gherman, Valentin

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Memory Reliability Improvement Based on Maximized Error-Correcting Codes by Gherman, Valentin, Evain, Samuel, Bonhomme, Yannick

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Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics by Gherman, Valentin, Farjallah, Emna, Armani, Jean-Marc, Seif, Marcelino, Dilillo, Luigi

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Programmable extended SEC-DED codes for memory errors by Gherman, V, Evain, S, Auzanneau, F, Bonhomme, Y

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Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection by Sarrazin, Sebastien, Evain, Samuel, de Barros Naviner, Lirida Alves, Bonhomme, Yannick, Gherman, Valentin

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System-level hardware-based protection of memories against soft-errors by Gherman, V., Evain, S., Cartron, M., Seymour, N., Bonhomme, Y.

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Error-correction schemes with erasure information for fast memories by Evain, Samuel, Gherman, Valentin

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Efficient pattern mapping for deterministic logic BIST by Gherman, V., Wunderlich, H.-J., Vranken, H., Hapke, F., Wittke, M., Garbers, M.

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Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps by Seif, Marcelino, Farjallah, Emna, Badets, Franck, Chabchoub, Emna, Layer, Christophe, Armani, Jean-Marc, Joffre, Francis, Anghel, Costin, Dilillo, Luigi, Gherman, Valentin

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Generalized parity-check matrices for SEC-DED codes with fixed parity by Gherman, V., Evain, S., Seymour, N., Bonhomme, Y.

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Implementing a scheme for external deterministic self-test by Hakmi, A.W., Wunderlich, H.-J., Gherman, V., Garbers, M., Schloffel, J.

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Memory reliability improvements based on maximized error-correcting codes by Gherman, V., Evain, S., Bonhomme, Y.

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Flip-Flop Selection for In-Situ Slack-Time Monitoring based on the Activation Probability of Timing-Critical Paths by Sarrazin, Sebastien, Evain, Samuel, Miro-Panades, Ivan, de Barros Naviner, Lirida Alves, Gherman, Valentin

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