Search Results - Givelin, P.

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  1. 1
    Determination of the ESD Failure Cause Through its Signature

    Determination of the ESD Failure Cause Through its Signature by Zecri, M., Besse, P., Givelin, P., Nayrolles, M., Bafleur, M., Nolhier, N.

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  2. 2
    The mirrored lateral SCR (MILSCR) as an ESD protection structure: design and optimization using 2-D device simulation

    The mirrored lateral SCR (MILSCR) as an ESD protection structure: design and optimization using 2-D device simulation by Delage, C., Nolhier, N., Bafleur, M., Dorkel, J.-M., Hamid, H., Givelin, P., Lin-Kwang, J.

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  3. 3
    An analysis of bipolar breakdown and its application to the design of ESD protection circuits

    An analysis of bipolar breakdown and its application to the design of ESD protection circuits by Joshi, S., Ida, R., Givelin, P., Rosenbaum, E.

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  4. 4
    Application of a floating well concept to a latch-up-free, low-cost, smart power high-side switch technology

    Application of a floating well concept to a latch-up-free, low-cost, smart power high-side switch technology by Bafleur, M., Buxo, J., Vidal, M.P., Givelin, P., Macary, V., Sarrabayrouse, G.

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  5. 5
    The Mirrored Lateral SCR (MILSCR) as an ESD protection structure for smart power applications

    The Mirrored Lateral SCR (MILSCR) as an ESD protection structure for smart power applications by Delage, C., Nolhier, N., Bafleur, M., Dorkel, J.M., Hamid, J., Givelin, P., Lin-Kwang, J.

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  6. 6
    Design and applications of an easily integrable CMOS operational floating amplifier for the MegaHertz range

    Design and applications of an easily integrable CMOS operational floating amplifier for the MegaHertz range by Laopoulos, Th, Siskos, S., Bafleur, M., Givelin, Ph, Tournier, E.

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  7. 7
    Cost-effective smart power CMOS/DMOS technology: design methodology for latch-up immunity

    Cost-effective smart power CMOS/DMOS technology: design methodology for latch-up immunity by Bafleur, M., Vidal, M. Puig, Buxo, J., Givelin, Ph, Macary, V., Sarrabayrouse, G.

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  8. 8
    Cost-effective smart power CMOS/DMOS technology: design of main driving and protection functions

    Cost-effective smart power CMOS/DMOS technology: design of main driving and protection functions by Bafleur, M., Givelin, Ph, Vidal, M. Puig, Buxo, J., Macary, V., Siskos, S., Laopoulos, Th

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