Search Results - Gurkaynak, F.

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  1. 1
    Power-analysis attack on an ASIC AES implementation

    Power-analysis attack on an ASIC AES implementation by Ors, S.B., Gurkaynak, F., Oswald, E., Preneel, B.

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  2. 2
    Improving DPA security by using globally-asynchronous locally-synchronous systems

    Improving DPA security by using globally-asynchronous locally-synchronous systems by Gurkaynak, F., Oetiker, S., Kaeslin, H., Felber, N., Fichtner, W.

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  3. 3
    A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic

    A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic by Hatirnaz, I, Gurkaynak, F K, Leblebici, Y

    Published in VLSI Design
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  4. 4
    A compact modular architecture for high-speed binary sorting

    A compact modular architecture for high-speed binary sorting by Hatirnaz, I., Gurkaynak, F.K., Leblebici, Y.

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  5. 5
    Improving the power-delay product in SCL circuits using source follower output stage

    Improving the power-delay product in SCL circuits using source follower output stage by Tajalli, Armin, Gurkaynak, Frank K., Leblebici, Yusuf, Alioto, Massimo, Brauer, Elizabeth J.

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  6. 6
    Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook

    Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook by Krstic, M., Grass, E., Gurkaynak, F.K., Vivet, P.

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  7. 7
    Towards an AES crypto-chip resistant to differential power analysis

    Towards an AES crypto-chip resistant to differential power analysis by Pramstaller, N., Gurkaynak, F.K., Haene, S., Kaeslin, H., Felber, N., Fichtner, W.

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  8. 8
    CONVOLVE: Smart and seamless design of smart edge processors

    CONVOLVE: Smart and seamless design of smart edge processors by Gomony, M, Putter, F, Gebregiorgis, A, Paulin, G, Mei, L, Jain, V, Hamdioui, S, Sanchez, V, Grosser, T, Geilen, M, Verhelst, M, Zenke, F, Gurkaynak, F, Bruin, B, Stuijk, S, Davidson, S, S De, Ghogho, M, Jimborean, A, Eissa, S, Benini, L, Soudris, D, Bishnoi, R, Ainsworth, S, Corradi, F, Karrakchou, O, Güneysu, T, Corporaal, H

    Published in arXiv.org
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  9. 9
    Area, throughput and security considerations for AES crypto-ASICs

    Area, throughput and security considerations for AES crypto-ASICs by Gurkaynak, F.K., Felber, N., Kaeslin, H., Fichtner, W.

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  10. 10
    Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture

    Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture by Constantin, Jeremy H.-F, Burg, A. P., Gurkaynak, F. K.

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  11. 11
    Efficient ASIC implementation of a real-time depth mapping stereo vision system

    Efficient ASIC implementation of a real-time depth mapping stereo vision system by Kuhn, M., Moser, S., Isler, O., Gurkaynak, F.K., Burg, A., Felber, N., Kaeslin, H., Fichtner, W.

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  12. 12
    Self-timed ring for globally-asynchronous locally-synchronous systems

    Self-timed ring for globally-asynchronous locally-synchronous systems by Villiger, T., Kaslin, H., Gurkaynak, F.K., Oetiker, S., Fichtner, W.

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  13. 13
    A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering

    A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering by Hatirnaz, I., Gurkaynak, F.K., Leblebici, Y.

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  14. 14
    A functional test methodology for globally-asynchronous locally-synchronous systems

    A functional test methodology for globally-asynchronous locally-synchronous systems by Gurkaynak, F.K., Villiger, T., Oetiker, S., Felber, N., Kaeslin, H., Fichtner, W.

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  15. 15
    A modular and scalable architecture for the realization of high-speed programmable rank order filters

    A modular and scalable architecture for the realization of high-speed programmable rank order filters by Hatirnaz, I., Gurkaynak, F.K., Leblebici, Y.

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  16. 16
    Modular realization of threshold logic gates for high performance digital signal processing applications

    Modular realization of threshold logic gates for high performance digital signal processing applications by Leblebici, Y., Gurkaynak, F.K.

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  17. 17
    Realization of a programmable rank-order filter architecture using capacitive threshold logic gates

    Realization of a programmable rank-order filter architecture using capacitive threshold logic gates by Hatirnaz, I., Gurkaynak, F.K., Leblebici, Y.

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  18. 18
    A compact 31-input programmable majority gate based on capacitive threshold logic

    A compact 31-input programmable majority gate based on capacitive threshold logic by Leblebici, Y., Gurkaynak, F.K., Mlynek, D.

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  19. 19
    EP-1563: Comparison of 3-dimensional conformal radiotherapy and intensity modulated radiotherapy for breast cancer

    EP-1563: Comparison of 3-dimensional conformal radiotherapy and intensity modulated radiotherapy for breast cancer by Kivanc, H, Gultekin, M, Yildiz, F, Gurkaynak, M

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  20. 20
    Hypofractionated radiotherapy for non-metastatic bone and soft tissue sarcomas

    Hypofractionated radiotherapy for non-metastatic bone and soft tissue sarcomas by Yuce Sari, S., Cengiz, M., Dauletkazin, A., Yazici, G., Gultekin, M., Hurmuz, P., Yildiz, F., Zorlu, F., Gurkaynak, M., Akyol, F., Ozyigit, G.

    Published in Cancer radiothérapie
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