Search Results - Gurkaynak, Frank K.

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  1. 1
    Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning

    Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning by Wistoff, Nils, Schneider, Moritz, Gurkaynak, Frank K., Heiser, Gernot, Benini, Luca

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  2. 2
    An Extended Shared Logarithmic Unit for Nonlinear Function Kernel Acceleration in a 65-nm CMOS Multicore Cluster

    An Extended Shared Logarithmic Unit for Nonlinear Function Kernel Acceleration in a 65-nm CMOS Multicore Cluster by Gautschi, Michael, Schaffner, Michael, Gurkaynak, Frank K., Benini, Luca

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  3. 3
    A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets

    A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets by Schuiki, Fabian, Schaffner, Michael, Gurkaynak, Frank K., Benini, Luca

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  4. 4
    Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes

    Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes by Schiavone, Pasquale Davide, Rossi, Davide, Di Mauro, Alfio, Gurkaynak, Frank K., Saxe, Timothy, Wang, Mao, Yap, Ket Chong, Benini, Luca

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  5. 5
    Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDW

    Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDW by Schaffner, Michael, Gurkaynak, Frank K., Greisen, Pierre, Kaeslin, Hubert, Benini, Luca, Smolic, Aljosa

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  6. 6
    Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core

    Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core by Wistoff, Nils, Schneider, Moritz, Gurkaynak, Frank K., Benini, Luca, Heiser, Gernot

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  7. 7
    Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices

    Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices by Gautschi, Michael, Schiavone, Pasquale Davide, Traber, Andreas, Loi, Igor, Pullini, Antonio, Rossi, Davide, Flamand, Eric, Gurkaynak, Frank K., Benini, Luca

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  8. 8
    High-efficiency logarithmic number unit design based on an improved cotransformation scheme

    High-efficiency logarithmic number unit design based on an improved cotransformation scheme by Popoff, Youri, Scheidegger, Florian, Schaffner, Michael, Gautschi, Michael, Gurkaynak, Frank K., Benini, Luca

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  9. 9
    A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology

    A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology by Rossi, Davide, Pullini, Antonio, Loi, Igor, Gautschi, Michael, Gürkaynak, Frank K., Bartolini, Andrea, Flatresse, Philippe, Benini, Luca

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  10. 10
    A current sensing completion detection method for asynchronous pipelines operating in the sub-threshold regime

    A current sensing completion detection method for asynchronous pipelines operating in the sub-threshold regime by Akgun, Omer Can, Gürkaynak, Frank K., Leblebici, Yusuf

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  11. 11
    Security, Reliability and Test Aspects of the RISC-V Ecosystem

    Security, Reliability and Test Aspects of the RISC-V Ecosystem by Abella, Jaume, Alcaide, Sergi, Anders, Jens, Bas, Francisco, Becker, Steffen, De Mulder, Elke, Elhamawy, Nourhan, Gurkaynak, Frank K., Handschuh, Helena, Hernandez, Carles, Hutter, Mike, Kosmidis, Leonidas, Polian, Ilia, Sauer, Matthias, Wagner, Stefan, Regazzoni, Francesco

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  12. 12
    Accuracy and Performance Trade-Offs of Logarithmic Number Units in Multi-Core Clusters

    Accuracy and Performance Trade-Offs of Logarithmic Number Units in Multi-Core Clusters by Schaffner, Michael, Gautschi, Michael, Gurkaynak, Frank K., Benini, Luca

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  13. 13
    Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET

    Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Float... by Paulin, Gianna, Scheffler, Paul, Benz, Thomas, Cavalcante, Matheus, Fischer, Tim, Eggimann, Manuel, Zhang, Yichao, Wistoff, Nils, Bertaccini, Luca, Colagrande, Luca, Ottavi, Gianmarco, Gurkaynak, Frank K., Rossi, Davide, Benini, Luca

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  14. 14
    XwattPilot: A Full-stack Cloud System Enabling Agile Development of Transprecision Software for Low-power SoCs

    XwattPilot: A Full-stack Cloud System Enabling Agile Development of Transprecision Software for Low-power SoCs by Diamantopoulos, Dionysios, Scheidegger, Florian, Mach, Stefan, Schuiki, Fabian, Haugou, Germain, Schaffner, Michael, Gurkaynak, Frank K., Hagleitner, Christoph, Malossi, A. Cristiano I., Benini, Luca

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  15. 15
    DRAM or no-DRAM? Exploring linear solver architectures for image domain warping in 28 nm CMOS

    DRAM or no-DRAM? Exploring linear solver architectures for image domain warping in 28 nm CMOS by Schaffner, Michael, Gurkaynak, Frank K., Smolic, Aljoscha, Benini, Luca

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  16. 16
    High speed ASIC implementations of leakage-resilient cryptography

    High speed ASIC implementations of leakage-resilient cryptography by Schilling, Robert, Unterluggauer, Thomas, Mangard, Stefan, Gurkaynak, Frank K., Muehlberghuber, Michael, Benini, Luca

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  17. 17
    An approximate computing technique for reducing the complexity of a direct-solver for sparse linear systems in real-time video processing

    An approximate computing technique for reducing the complexity of a direct-solver for sparse linear systems in real-time video processing by Schaffner, Michael, Gurkaynak, Frank K., Smolic, Aljosa, Kaeslin, Hubert, Benini, Luca

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  18. 18
    4.6 A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster

    4.6 A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster by Gautschi, Michael, Schaffner, Michael, Gurkaynak, Frank K., Benini, Luca

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  19. 19
    MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping

    MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping by Schaffner, Michael, Greisen, Pierre, Heinzle, Simon, Gurkaynak, Frank K., Kaeslin, Hubert, Smolic, Aljoscha

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  20. 20
    GALS at ETH Zurich: success or failure?

    GALS at ETH Zurich: success or failure? by Gurkaynak, F.K., Oetiker, S., Kaeslin, H., Felber, N., Fichtner, W.

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