A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs by Matakias, S, Tsiatouhas, Y, Arapoyanni, A, Haniotakis, Th

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Domino CMOS SCD/SFS 2-out-of-3 and 1-out-of-3 code checkers by Haniotakis, Th, Tsiatouhas, Y., Efstathiou, C., Nikolos, D.

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A new technique for IDDQ testing in nanometer technologies by Tsiatouhas, Y., Moisiadis, Y., Haniotakis, Th, Nikolos, D., Arapoyanni, A.

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A built-in I/sub DDQ/ testing circuit by Matakias, S., Tsiatouhas, Y., Arapoyanni, A., Haniotakis, Th, Prenat, G., Mir, S.

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A concurrent BIST architecture based on Monitoring Square Windows by Voyiatzis, I, Haniotakis, T, Efstathiou, C, Antonopoulou, H

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Path delay fault testing of multiplexer-based shifters by Vergos, H. T., Tsiatouhas, Y., Haniotakis, Th, Nikolos, D., Nicolaidis, M.

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A versatile built-in self test scheme for delay fault testing by Tsiatouhas, Y., Haniotakis, Th, Nikolos, D., Arapoyanni, A.

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Testable designs of one-count generators by HANIOTAKIS, TH, PASCHALIS, A., HALATSIS, C., PHILOKYPROU, G.

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A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism by Floros, A., Tsiatouhas, Y., Arapoyanni, A., Haniotakis, T.

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C-testable one-dimensional ILAs with respect to path delay faults: theory and applications by Haniotakis, Th, Tsiatouhas, Y., Nikolos, D.

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Hierarchical robust test generation for CMOS circuit stuck-open faults by TSIATOUHAS, Y., HANIOTAKIS, TH, NIKOLOS, D., PASCHALIS, A., HALATSIS, C.

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Totally self-checking checkers for Borden codes by HANIOTAKIS, TH, NIKOLOS, D., PASCHALIS, A., GIZOPOULOS, D.

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The use of pre-evaluation phase in dynamic CMOS logic by Rao, A., Haniotakis, Th, Tsiatouhas, Y., Djemil, H.

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Fast, parallel two-rail code checker with enhanced testability by Matakias, S., Arapoyanni, A., Efthymiou, A., Tsiatouhas, Y., Haniotakis, T.

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A new dynamic circuit design technique for high performance TSC checker implementations [totally self checking circuits] by Rao, A., Haniotakis, T., Tsiatouhas, Y., Kaky, V.

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A sense amplifier based circuit for concurrent detection of soft and timing errors in CMOS ICs by Tsiatouhas, Y., Matakias, S., Arapoyanni, A., Haniotakis, Th

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A hierarchical architecture for concurrent soft error detection based on current sensing by Tsiatouhas, Y., Arapoyanni, A., Nikolos, D., Haniotakis, T.

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Ultra fast and low cost parallel two-rail code checker targeting high fan-in applications by Matakias, S., Tsiatouhas, Y., Haniotakis, Th, Arapoyanni, A.

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A low power NORA circuit design technique based on charge recycling by Tsiatouhas, Y., Limniotis, K., Arapoyanni, A., Haniotakis, T.

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On testability of multiple precharged domino logic by Haniotakis, T., Tsiatouhas, Y., Nikolos, D., Efstathiou, C.

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