A Delay-Locked Loop Synchronization Scheme for High-Frequency Multiphase Hysteretic DC-DC Converters by Pengfei Li, Lin Xue, Hazucha, P., Karnik, T., Bashirullah, R.

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Impact of CMOS technology scaling on the atmospheric neutron soft error rate by Hazucha, P., Svensson, C.

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Characterization of soft errors caused by single event upsets in CMOS processes by Karnik, T., Hazucha, P.

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Area-efficient linear regulator with ultra-fast load regulation by Hazucha, P., Karnik, T., Bloechel, B.A., Parsons, C., Finan, D., Borkar, S.

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A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package by Hazucha, P., Schrom, G., Jaehong Hahn, Bloechel, B.A., Hack, P., Dermer, G.E., Narendra, S., Gardner, D., Karnik, T., De, V., Borkar, S.

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Integrated on-chip inductors using magnetic material (invited) by Gardner, Donald S., Schrom, Gerhard, Hazucha, Peter, Paillet, Fabrice, Karnik, Tanay, Borkar, Shekhar, Hallstein, Roy, Dambrauskas, Tony, Hill, Charles, Linde, Clark, Worwag, Wojciech, Baresel, Robert, Muthukumar, Sriram

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Integrated On-Chip Inductors With Magnetic Films by Gardner, D.S., Schrom, G., Hazucha, P., Paillet, F., Karnik, T., Borkar, S.

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High-voltage power delivery through charge recycling by Rajapandian, S., Shepard, K.L., Hazucha, P., Karnik, T.

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High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters by Hazucha, P., Sung Tae Moon, Schrom, G., Paillet, F., Gardner, D., Rajapandian, S., Karnik, T.

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Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/T/ CMOS process by Hazucha, P, Karnik, T, Walstra, S, Bloechel, B A, Tschanz, J W, Maiz, J, Soumyanath, K, Dermer, G E, Narendra, S, De, V, Borkar, S

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Cosmic-ray soft error rate characterization of a standard 0.6- mu m CMOS process by Hazucha, P, Svensson, C, Wender, SA

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A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction by Jianping Xu, Hazucha, P., Zuoguo Wu, Aseron, P., Mingwei Huang, Paillet, F., Schrom, G., Tschanz, J., De, V., Karnik, T., Taylor, G.

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Cosmic ray neutron multiple-upset measurements in a 0.6 micron CMOS process by Hazucha, Peter, Svensson, Christer

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Cosmic ray neutron multiple-upset measurements in a 0.6- mu m CMOS process by Hazucha, P, Svensson, C

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Optimized test circuits for SER characterization of a manufacturing process by Hazucha, P., Svensson, C.

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On-Die Supply-Resonance Suppression Using Band-Limited Active Damping by Xu, Jianping, Hazucha, Peter, Huang, Mingwei, Aseron, Paolo, Paillet, Fabrice, Schrom, Gerhard, Tschanz, James, Zhao, Cangsang, De, Vivek, Karnik, Tanay, Taylor, Greg

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Neutron induced soft errors in CMOS memories under reduced bias by Hazucha, P., Johansson, K., Svensson, C.

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High-frequency DC-DC conversion : fact or fiction by Karnik, T., Hazucha, P., Schrom, G., Paillet, F., Gardner, D.

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Measurements and analysis of SER-tolerant latch in a 90-nm Dual-VT CMOS process by HAZUCHA, Peter, KARNIK, Tanay, BORKAR, Shekhar, WALSTRA, Steven, BLOECHEL, Bradley A, TSCHANZ, James W, MAIZ, Jose, SOUMYANATH, Krishnamurthy, DERMER, Gregory E, NARENDRA, Siva, DE, Vivek

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A 233-MHz 80% efficient four-phase DC-DC converter utilizing air-core inductors on package by HAZUCHA, Peter, SCHROM, Gerhard, BORKAR, Shekhar, HAHN, Jaehong, BLOECHEL, Bradley A, HACK, Paul, DERMER, Gregory E, NARENDRA, Siva, GARDNER, Donald, KARNIK, Tanay, DE, Vivek

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