A low damage Si3N4 sidewall spacer process for self-aligned sub-100 nm III-V MOSFETs by LI, X, HILL, R. J. W, ZHOU, H, WILKINSON, C. D. W, THAYNE, I. G

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Simulation of implant free III-V MOSFETs for high performance low power Nano-CMOS applications by Asenov, A., Kalna, K., Thayne, I., Hill, R.J.W.

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Dry etching device quality high-κ GaxGdyOz gate oxide in SiCl4 chemistry for low resistance ohmic contact realisation in fabricating III-V MOSFETs by LI, X, ZHOU, H, HILL, R. J. W, LONGO, P, HOLLAND, M, THAYNE, I. G

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EFTEM and EELS SI: tools for investigating the effects of etching processes for III-V MOSFET devices by Longo, P, Scott, J, Craven, A J, Hill, R J W, Thayne, I G

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Dry etching of a device quality high-k GaxGdyOz gate oxide in CH4/H2-O2 chemistry for the fabrication of III-V MOSFETs by LI, X, ZHOU, H, HILL, R. J. W, WILKINSON, C. D. W, THAYNE, I. G

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Compound semiconductors on silicon for future generation VLSI by Hill, R J W, Baraskar, A, Park, C, Barnett, J, Majhi, P, Jammy, R

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High-Speed E-Mode InAs QW MOSFETs With \hbox \hbox Insulator for Future RF Applications by Dae-Hyun Kim, Tae-Woo Kim, Hill, R. J. W., Young, C. D., Chang Yong Kang, Hobbs, C., Kirsch, P., del Alamo, J. A., Jammy, R.

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(Invited) Integration Challenges of III-V Materials in Advanced CMOS Logic by Hill, Richard J., Huang, Jeff, Loh, Wei Yip, Kim, Taewoo, Wong, M. H., Veksler, D., Cunningham, T. H., Droopad, R., Oh, Jungwoo, Hobbs, Chris, Kirsch, Paul D., Jammy, Raj

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Review of Current Status of III-V MOSFETs by Thayne, Iain, Hill, Richard, Holland, Martin, Li, Xi, Zhou, Haiping, Macintyre, Douglas, Thoms, Stephen, Kalna, Karol, Stanley, Colin, Asenov, Asen, Droopad, Ravi, Passlack, Matthias

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CMOS Scaling with III-V Channels for Improved Performance and Low Power by Hill, Richard J., Oh, Jungwoo, Park, Chanro, Barnett, J., Price, Jimmy, Huang, Jeff, Goel, Niti, Loh, W. Y., Kirsch, Paul, Majhi, Prashant, Jammy, Raj

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Sub-100 nm regrown S/D Gate-Last In0.7Ga0.3As QW MOSFETs with μn,eff > 5,500 cm2/V-s by Shin, C-S, Park, W-K, Shin, S. H., Cho, Y. D., Ko, D. H., Kim, T-W, Koh, D. H., Kwon, H. M., Hill, R. J. W., Kirsch, P., Maszara, W., Kim, D-H

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Challenges of III-V materials in advanced CMOS logic by Kirsch, P. D., Hill, R. J. W., Huang, J., Loh, W. Y., Kim, T.-W, Wong, M. H., Min, B. G., Huffman, C., Veksler, D., Young, C. D., Ang, K. W., Ali, I., Lee, R. T. P., Ngai, T., Wang, A., Wang, W.-E, Cunningham, T. H., Chen, Y. T., Hung, P. Y., Bersch, E., Sassman, B., Cruz, M., Trammell, S., Droopad, R., Oktybrysky, S., Lee, J. C., Bersuker, G., Hobbs, C., Jammy, R.

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InAs quantum-well MOSFET (Lg = 100 nm) with record high gm, fT and fmax by Kim, T.-W, Hill, R. J. W., Young, C. D., Veksler, D., Morassi, L., Oktybrshky, S., Oh, J., Kang, C. Y., Kim, D., del Alamo, J. A., Hobbs, C., Kirsch, P. D., Jammy, R.

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Monte Carlo Simulations of High-Performance Implant Free In0.3Ga 0.7As Nano-MOSFETs for Low-Power CMOS Applications by Kalna, K, Wilson, J. A, Moran, D. A. J, Hill, R. J. W, Long, A. R, Droopad, R, Passlack, M, Thayne, I. G, Asenov, A

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High Mobility III-V MOSFETs For RF and Digital Applications by Passlack, M., Zlotnicka, A., Fejes, P., Hill, R.J.W., Moran, D.A.J., Li, X., Zhou, H., Macintyre, D., Thoms, S., Asenov, A., Kalna, K., Zurcher, P., Thayne, I.G., Rajagopalan, K., Droopad, R., Abrokwah, J., Tutt, M., Park, Y.-B., Johnson, E., Hartin, O.

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Ultra low contact resistivity (−8 Ω-cm2) to In0.53Ga0.47As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III-V fin TLM structure fabricated with III-V on Si sub... by Lee, Rinus T. P., Ohsawa, Y., Huffman, C., Trickett, Y., Nakamura, G., Hatem, C., Rao, K. V., Khaja, F., Lin, R., Matthews, K., Dunn, K., Jensen, A., Karpowicz, T., Nielsen, Peter F., Stinzianni, E., Cordes, A., Hung, P. Y., Kim, D-H, Hill, R. J. W., Loh, W-Y, Hobbs, C.

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ETB-QW InAs MOSFET with scaled body for improved electrostatics by Kim, T.-W, Kim, D., Koh, D.-H, Hill, R. J. W., Lee, R. T. P., Wong, M. H., Cunningham, T., del Alamo, J. A., Banerjee, S. K., Oktyabrsky, S., Greene, A., Ohsawa, Y., Trickett, Y., Nakamura, G., Li, Q., Lau, K. M., Hobbs, C., Kirsch, P. D., Jammy, R.

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VLSI processed InGaAs on Si MOSFETs with thermally stable, self-aligned Ni-InGaAs contacts achieving: Enhanced drive current and pathway towards a unified contact module by Lee, Rinus T. P., Hill, R. J. W., Loh, W.-Y, Baek, R.-H, Deora, S., Matthews, K., Huffman, C., Majumdar, K., Michalak, T., Borst, C., Hung, P. Y., Chen, C.-H, Yum, J.-H, Kim, T.-W, Kang, C. Y., Wei-E Wang, Kim, D.-H, Hobbs, C., Kirsch, P. D.

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Effect of ALD oxidant and channel doping on positive bias stress characteristics of surface channel In0.53Ga0.47As nMOSFETs by Young, C. D., Hill, R. J. W., Matthews, K., Wang, W., Hinkle, C., Wallace, R. M., Loh, W., Hobbs, C., Kirsch, P. D., Jammy, R.

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Sub-10nm junction in InGaAs with sulfur mono-layer doping by Loh, W.-Y, Wang, W.-E, Hill, R. J. W., Barnett, J., Yum, J. H., Lysagth, P., Price, J., Hung, P. Y., Kirsch, P. D., Jammy, R.

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