Stress Modulation of Silicon Nitride Film by Initial Deposition Conditions for Transistor Carrier Mobility Enhancement by Tian, Jingze, Zuo, Biao, Lu, Wei, Zhou, Meisheng, Hsia, Liang Choo

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Underfill selection methodology for fine pitch Cu/low-k FCBGA packages by Ong, Xuefen, Ho, Soon Wee, Ong, Yue Ying, Wai, Leong Ching, Vaidyanathan, Kripesh, Lim, Yeow Kheng, Yeo, David, Chan, Kai Chong, Tan, Juan Boon, Sohn, Dong Kyun, Hsia, Liang Choo, Chen, Zhong

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Wafer level microarcing model in 90nm chemical-vapor deposition low-k via etch on 300mm silicon-on-insulator substrate by Cong, Hai, Low, Chun Hui, Pradeep, Yelehanka Ramachandramurthy, Zhang, Xin, Chandima, Perera, Liu, Wu Ping, Tan, Juan Boon, Hsia, Liang Choo

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Wafer level microarcing model in 90 nm chemical-vapor deposition low- k via etch on 300 mm silicon-on-insulator substrate by Cong, Hai, Low, Chun Hui, Pradeep, Yelehanka Ramachandramurthy, Zhang, Xin, Chandima, Perera, Liu, Wu Ping, Tan, Juan Boon, Hsia, Liang Choo

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Towards Unification of MOS Compact Models with the Unified Regional Approach by Rustagi, Subhash, See, Guan Huei, Chandrasekaran, K., Zhou, Xing, Hsia, Liang-Choo, Chu, Sanford, Cheng, M., Chiah, Siau Ben, Wei, Chengqing, Lin, Shihuan, Lim, Guan Hui, Zhu, Zhaomin

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BEOL Advance Interconnect Technology Overview and Challenges by Liang Choo Hsia, Tan, J.B., Bei Chao Zhang, Wu Ping Liu, Yeow Kheng Lim, Dong Kyun Sohn

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Integration of a poisoning-free dual damascene CDO film stack for 90 nm & beyond low-k BEOL by Wu Ping Liu, Juan Boon Tan, Wei Lu, Shyam Pal, Yong Kong Siew, Hai Cong, Bei Chao Zhang, Xian Bin Wang, Fan Zhang, Liang Choo Hsia

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Effects of X-ray irradiation on GIDL in MOSFETs by Acovic, A., Hsu, C.C.-H., Hsia, L.-C., Balasinski, A., Ma, T.-P.

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Challenges in sub-0.13 /spl mu/m front-end-of-line processes by Jia-Zhen Zheng, Liang-Choo Hsia

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Structural Design and Optimization of 65nm Cu/low-k Flipchip Package by Ong, Jimmy, Tay, Andrew, Zhang, Xiaowu, Kripesh, V., Lim, Yeow Kheng, Yeo, David, Chan, Kai Chong, Tan, Juan Boon, Hsia, Liang Choo, Sohn, Dong Kyun

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A Systematic Underfill Selection Methodology for Fine Pitch Cu/Low-k FCBGA Package by Ong, Xuefen, Sohn, Dong Kyun, Hsia, Liang Choo, Chen, Zhong, Ho, Soon Wee, Ong, Yue Ying, Wai, Leong Ching, Vaidyanathan, Kripesh, Lim, Yeow Kheng, Yeo, David, Chan, Kai Chong, Tan, Juan Boon

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A novel approach for dual damascene trench etch for 90nm low-K interconnect with no middle etch stop layer by CHEN, Tong Qing, CONG, Hai, LIU, Wu Ping, SIEW, Yong Kong, PRADEEP, Yelehanka, HSIA, Liang Choo, JAISWAL, Rakesh, JAIN, Alok, SIM, Ivan

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Trench etch: Optimization with 193 nm resist by Yong Kong Siew, Joy, Raymond, Tan, Dennis, Liu, Wuping

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