A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs by Matakias, S, Tsiatouhas, Y, Arapoyanni, A, Haniotakis, Th

Get full text

Domino CMOS SCD/SFS 2-out-of-3 and 1-out-of-3 code checkers by Haniotakis, Th, Tsiatouhas, Y., Efstathiou, C., Nikolos, D.

Get full text

A new technique for IDDQ testing in nanometer technologies by Tsiatouhas, Y., Moisiadis, Y., Haniotakis, Th, Nikolos, D., Arapoyanni, A.

Get full text

A built-in I/sub DDQ/ testing circuit by Matakias, S., Tsiatouhas, Y., Arapoyanni, A., Haniotakis, Th, Prenat, G., Mir, S.

Request full text

Path delay fault testing of multiplexer-based shifters by Vergos, H. T., Tsiatouhas, Y., Haniotakis, Th, Nikolos, D., Nicolaidis, M.

Get full text

A versatile built-in self test scheme for delay fault testing by Tsiatouhas, Y., Haniotakis, Th, Nikolos, D., Arapoyanni, A.

Request full text

Testable designs of one-count generators by HANIOTAKIS, TH, PASCHALIS, A., HALATSIS, C., PHILOKYPROU, G.

Get full text

A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism by Floros, A., Tsiatouhas, Y., Arapoyanni, A., Haniotakis, T.

Request full text

C-testable one-dimensional ILAs with respect to path delay faults: theory and applications by Haniotakis, Th, Tsiatouhas, Y., Nikolos, D.

Request full text

Hierarchical robust test generation for CMOS circuit stuck-open faults by TSIATOUHAS, Y., HANIOTAKIS, TH, NIKOLOS, D., PASCHALIS, A., HALATSIS, C.

Get full text

Totally self-checking checkers for Borden codes by HANIOTAKIS, TH, NIKOLOS, D., PASCHALIS, A., GIZOPOULOS, D.

Get full text

The use of pre-evaluation phase in dynamic CMOS logic by Rao, A., Haniotakis, Th, Tsiatouhas, Y., Djemil, H.

Request full text

A sense amplifier based circuit for concurrent detection of soft and timing errors in CMOS ICs by Tsiatouhas, Y., Matakias, S., Arapoyanni, A., Haniotakis, Th

Request full text

Ultra fast and low cost parallel two-rail code checker targeting high fan-in applications by Matakias, S., Tsiatouhas, Y., Haniotakis, Th, Arapoyanni, A.

Request full text

Device simulation of a n-DMOS cell with trench isolation by Kamoulakos, G, Haniotakis, Th, Tsiatouhas, Y, Schoellkopf, J.-P, Arapoyanni, A

Get full text

Extending the viability of I/sub DDQ/ testing in the deep submicron era by Tsiatouhas, Y., Haniotakis, Th, Nicolos, D., Arapoyanni, A.

Request full text

SRAM oriented memory sense amplifier design in 0.18 /spl mu/m CMOS technology by Chrisanthopoulos, A., Tsiatouhas, Y., Arapoyanni, A., Haniotakis, Th

Request full text

On path delay fault testing of multiplexer-based shifters by Vergos, H.T., Tsiatouhas, Y., Haniotakis, T., Nikolos, D., Nicolaidis, M.

Request full text