Search Results - Heloue, Khaled R.

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  1. 1
    Modeling and estimation of full-chip leakage current considering within-die correlation

    Modeling and estimation of full-chip leakage current considering within-die correlation by Heloue, Khaled R., Azizi, Navid, Najm, Farid N.

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  2. 2
    Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths

    Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths by Heloue, K. R., Onaissi, S., Najm, F. N.

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  3. 3
    Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models

    Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models by Heloue, K.R., Najm, F.N.

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  4. 4
    Full-Chip Model for Leakage-Current Estimation Considering Within-Die Correlation

    Full-Chip Model for Leakage-Current Estimation Considering Within-Die Correlation by Heloue, K.R., Azizi, N., Najm, F.N.

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  5. 5
    Efficient block-based parameterized timing analysis covering all potentially critical paths

    Efficient block-based parameterized timing analysis covering all potentially critical paths by Heloue, K.R., Onaissi, S., Najm, F.N.

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  6. 6
    Parameterized timing analysis with general delay models and arbitrary variation sources

    Parameterized timing analysis with general delay models and arbitrary variation sources by Heloue, Khaled R., Najm, Farid N.

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  7. 7
    Quantifying robustness metrics in parameterized static timing analysis

    Quantifying robustness metrics in parameterized static timing analysis by Heloue, K.R., Kashyap, C.V., Najm, F.N.

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  8. 8
    Clock skew optimization via wiresizing for timing sign-off covering all process corners

    Clock skew optimization via wiresizing for timing sign-off covering all process corners by Onaissi, Sari, Heloue, Khaled R., Najm, Farid N.

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  9. 9
    PSTA-based branch and bound approach to the silicon speedpath isolation problem

    PSTA-based branch and bound approach to the silicon speedpath isolation problem by Onaissi, S., Heloue, K.R., Najm, F.N.

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  10. 10
    Early Analysis of Timing Margins and Yield

    Early Analysis of Timing Margins and Yield by Heloue, Khaled R., Najm, Farid N.

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  11. 11
    Statistical timing analysis with two-sided constraints

    Statistical timing analysis with two-sided constraints by Heloue, K.R., Najm, F.N.

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  12. 12
    Effect of statistical clock skew variations on chip timing yield

    Effect of statistical clock skew variations on chip timing yield by Heloue, K.R., Najm, F.N.

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  13. 13
    Statistical timing analysis with two-sided constraints

    Statistical timing analysis with two-sided constraints by Heloue, K. R., Najm, F. N.

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