MUSTANG: state assignment of finite state machines targeting multilevel logic implementations by Devadas, S., Hi-Keung Ma, Newton, A.R., Sangiovanni-Vincentelli, A.

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A practical and efficient method for compare-point matching by Anastasakis, Demos, Damiano, Robert, Ma, Hi-Keung Tony, Stanion, Ted

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On the over-specification problem in sequential ATPG algorithms by Cheng, K.-T., Ma, H.-K.T.

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Redundancies and don't cares in sequential logic synthesis by Devadas, Srinivas, Ma, Hi-Keung Tony, Newton, A. Richard

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A practical and efficient method for compare-point matching by Anastasakis, D., Damiano, R., Ma, H.-K.T., Stanion, T.

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Test generation for sequential circuits by Ma, H.-K.T., Devadas, S., Newton, A.R., Sangiovanni-Vincentelli, A.

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Mixed-Level Fault Coverage Estimation by Hi Keung Ma, Sangiovanni-Vincentelli, A.L.

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Chameleon: A New Multi-Layer Channel Router by Braun, D., Burns, J., Devadas, S., Hi Keung Ma, Mayaram, K., Romeo, F., Sangiovanni-Vincentelli, A.

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Irredundant sequential machines via optimal logic synthesis by Devadas, S., Ma, H.-K.T., Newton, A.R., Sangiovanni-Vincentelli, A.

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A synthesis and optimization procedure for fully and easily testable sequential machines by Devadas, S., Ma, H.-K.T., Newton, A.R., Sangiovanni-Vincentelli, A.

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Easily testable PLA-based finite state machines by Devadas, S., Ma, H.-K.T.

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On the verification of sequential machines at differing levels of abstraction by Devadas, S., Ma, H.-K.T., Newton, A.R.

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Techniques for multilayer channel routing by Braun, D., Burns, J.L., Romeo, F., Sangiovanni-Vincentelli, A., Mayaram, K., Devadas, S., Ma, H.-K.T.

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A robust solution to the timing convergence problem in high-performance design by Shenoy, N., Iyer, M., Damiano, R., Harer, K., Hi-Keung Ma, Thilking, P.

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Logic verification algorithms and their parallel implementation by Ma, H.-K.T., Devadas, S., Ruey-Sing Wei, Sangiovanni-Vincentelli, A.

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Cell Swapping Based Migration Methodology for Analog and Custom Layouts by Batterywala, S.H., Bhattacharya, S., Rajagopalan, S., Ma, H.-K.T., Shenoy, N.V.

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On Efficient and Robust Constraint Generation for Practical Layout Legalization by Bhattacharya, S., Batterywala, S.H., Rajagopalan, S., Ma, H.-K.T., Shenoy, N.V.

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Report on 24th ACM/IEEE design automation conference by Ma, Hi-Keung

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Easily testable PLA-based finite state machines by Devadas, S., Ma, H.-K.T., Newton, A.R.

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On the over-specification problem in sequential ATPG algorithms by Cheng, K.-T., Ma, H.-K.T.

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