Search Results - Hibbeler, Jason

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  1. 1
    Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings

    Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings by Jhaveri, T., Rovner, V., Liebmann, L., Pileggi, L., Strojwas, A.J., Hibbeler, J.D.

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  2. 2
    The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking

    The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking by Fluhr, Eric J., Baumgartner, Steve, Boerstler, David, Bulzacchelli, John F., Diemoz, Timothy, Dreps, Daniel, English, George, Friedrich, Joshua, Gattiker, Anne, Gloekler, Tilman, Gonzalez, Christopher, Hibbeler, Jason D., Jenkins, Keith A., Yong Kim, Muench, Paul, Nett, Ryan, Paredes, Jose, Pille, Juergen, Plass, Donald, Restle, Phillip, Robertazzi, Raphael, Shan, David, Siljenberg, David, Sperling, Michael, Stawiasz, Kevin, Still, Gregory, Toprak-Deniz, Zeynep, Warnock, James, Wiedemeier, Glen, Zyuban, Victor

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  3. 3
    5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8TM microprocessor

    5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8TM microprocessor by Restle, Phillip, Shan, David, Hogenmiller, David, Yong Kim, Drake, Alan, Hibbeler, Jason, Bucelot, Thomas, Still, Gregory, Jenkins, Keith, Friedrich, Joshua

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  4. 4
    Optimizing product yield using manufacturing defect weights

    Optimizing product yield using manufacturing defect weights by Bickford, J. P., Hibbeler, J. D., Mueller, D., Peyer, Sven, Kumar, Vasanth S.

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  5. 5
    High-Value Design Techniques for Mitigating Random Defect Sensitivities

    High-Value Design Techniques for Mitigating Random Defect Sensitivities by Maynard, D.N., Rosner, R.J., Hibbeler, J.D., Culp, J.A., Barnett, T.S.

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  6. 6
    Moving Carefully Towards Model-based Layout Optimization and Checking

    Moving Carefully Towards Model-based Layout Optimization and Checking by Hibbeler, J.D., Maynard, D.N.

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  7. 7
    High-Value Design Techniques for Mitigating Random Defect Sensitivities : Advanced semiconductor manufacturing conference

    High-Value Design Techniques for Mitigating Random Defect Sensitivities : Advanced semiconductor manufacturing conference by MAYNARD, Daniel N, ROSNER, Raymond J, HIBBELER, Jason D, CULP, James A, BAMETT, Thomas S

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  8. 8
    Measurement and reduction of critical area using Voronoi diagrams

    Measurement and reduction of critical area using Voronoi diagrams by Maynard, D.N., Hibbeler, J.D.

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  9. 9
    Resonant clock mega-mesh for the IBM z13

    Resonant clock mega-mesh for the IBM z13 by Shan, David, Restle, Phillip, Malone, Doug, Groves, Rob, Lai, Eric, Koch, Michael, Hibbeler, Jason, Kim, Yong, Vezyrtzis, Christos, Feder, Jan, Hogenmiller, David, Bucelot, Thomas

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  10. 10
    Resonant clock mega-mesh for the IBM z13TM

    Resonant clock mega-mesh for the IBM z13TM by Shan, David, Restle, Phillip, Malone, Doug, Groves, Rob, Lai, Eric, Koch, Michael, Hibbeler, Jason, Yong Kim, Vezyrtzis, Christos, Feder, Jan, Hogenmiller, David, Bucelot, Thomas

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  11. 11
    Yield Improvement by Local Wiring Redundancy

    Yield Improvement by Local Wiring Redundancy by Bickford, Jeanne, Hibbeler, Jason, Buhler, Markus, Koehl, Jurgen, Muller3, Dirk, Peyer, Sven, Schulte, Christian

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