Search Results - Hsien-Nan Chiu

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  1. 1
    A novel poly-Si thin-film transistor with multi-trenched body by using Isotropic-etching for Suppressing Off-State Leakage

    A novel poly-Si thin-film transistor with multi-trenched body by using Isotropic-etching for Suppressing Off-State Leakage by Hsien-Nan Chiu, Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hiesh Lin, Tzu-Feng Chang, Chih-Hung Sun, Chih-Hao Kuo, Hsuan-Hsu Chen

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  2. 2
    Future of planar self-aligned block oxide based MOSFET technology

    Future of planar self-aligned block oxide based MOSFET technology by Jyi-Tsong Lin, Yi-Chuen Eng, Chih-Hao Kuo, Tzu-Feng Chang, Chih-Hung Sun, Po-Hsieh Lin, Hsien-Nan Chiu, Hsuan-Hsu Chen

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  3. 3
    A Novel Vertical MOSFET with bMPI Structure for 1T-DRAM Applications: A 2-D Numerical Study

    A Novel Vertical MOSFET with bMPI Structure for 1T-DRAM Applications: A 2-D Numerical Study by Chen, Cheng-Hsin, Lin, Jyi-Tsong, Eng, Yi-Chuen, Lin, Po-Hsieh, Chiu, Hsien-Nan, Chang, Tzu-Feng

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  4. 4
    A simple process of thin-film transistor using the trench-oxide layer for improving 1T-DRAM performance

    A simple process of thin-film transistor using the trench-oxide layer for improving 1T-DRAM performance by Hsien-Nan Chiu, Jyi-Tsong Lin, Yi-Chuen Eng, Tzu-Feng Chang, Cheng-Hsin Chen

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  5. 5
    A novel vertical MOSFET with bMPI structure for 1T-DRAM application

    A novel vertical MOSFET with bMPI structure for 1T-DRAM application by Cheng-Hsin Chen, Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hsieh Lin, Hsien-Nan Chiu, Tzu-Feng Chang, Chih-Hsuan Tai, Kuan-Yu Lu, Yi-Hsuan Fan, Yu-Che Chang, Hsuan-Hsu Chen

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  6. 6
    Numerical study of non-classical unipolar CMOS with different embedded oxide and gate length

    Numerical study of non-classical unipolar CMOS with different embedded oxide and gate length by Chih-Hung Sun, Jyi-Tsong Lin, Hsuan-Hsu Chen, Yi-Chuen Eng, Chih-Hao Kuo, Tze-Feng Chang, Chun-Yu Chen, Po-Hsieh Lin, Hsien-Nan Chiu

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  7. 7
    Reliability analysis of a new vertical MOSFET with bMPI structure for 1T-DRAM applications

    Reliability analysis of a new vertical MOSFET with bMPI structure for 1T-DRAM applications by Cheng-Hsin Chen, Jyi-Tsong Lin, Po-Hsieh Lin, Yi-Chuen Eng, Hsien-Nan Chiu, Tzu-Feng Chang, Hsuan-Hsu Chen

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  8. 8
    Characteristics of a new trench-oxide thin-film transistor and its 1T-DRAM applications

    Characteristics of a new trench-oxide thin-film transistor and its 1T-DRAM applications by Hsien-Nan Chiu, Jyi-Tsong Lin, Yi-Chuen Eng, Tzu-Feng Chang, Chih-Hung Sun, Po-Hiesh Lin, Chih-Hao Kuo, Hsuan-Hsu Chen, Cheng-Hsin Chen

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  9. 9
    Thermal characteristics of an advanced bMPI-based 1T-DRAM cell

    Thermal characteristics of an advanced bMPI-based 1T-DRAM cell by Cheng-Hsin Chen, Jyi-Tsong Lin, Yi-Chuen Eng, Hsien-Nan Chiu, Tzu-Feng Chang, Yi-Hsuan Fan, Yu-Che Chang, Kuan-Yu Lu, Chih-Hsuan Tai

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  10. 10
    Advanced block oxide MOSFETs for 25 nm technology node

    Advanced block oxide MOSFETs for 25 nm technology node by Chih-Hung Sun, Jyi-Tsong Lin, Yi-Chuen Eng, Tzu-Feng Chang, Po-Hiesh Lin, Hsuan-Hsu Chen, Chih-Hao Kuo, Hsien-Nan Chiu

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  11. 11
    A novel self-align double gate MOSFET with source/drain tie

    A novel self-align double gate MOSFET with source/drain tie by Po-Hsieh Lin, Jyi-Tsong Lin, Yi-Chuen Eng, Hsuan-Hsu Chen, Chih-Hao Kuo, Chih-Hung Sun, Hsien-Nan Chiu, Tzu-Feng Chang, Nai-Chuan Chuang

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  12. 12
    Improving reliability and diminishing parasitic capacitance effects in a vertical transistor with embedded gate

    Improving reliability and diminishing parasitic capacitance effects in a vertical transistor with embedded gate by Jyi-Tsong Lin, Chih-Hao Kuo, Tai-Yi Lee, Yi-Chuen Eng, Tzu-Feng Chang, Po-Hsieh Lin, Hsuan-Hsu Chen, Chih-Hung Sun, Hsien-Nan Chiu

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  13. 13
    Characteristics of a Local Oxidation of silicon multi-tie body polysilicon thin-film transistor

    Characteristics of a Local Oxidation of silicon multi-tie body polysilicon thin-film transistor by Hsien-Nan Chiu, Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hiesh Lin, Tzu-Feng Chang, Chih-Hung Sun, Hsuan-Hsu Chen, Chih-Hao Kuo

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  14. 14
    The impact of junction depth on vertical sidewall MOSFETs with embedded gate

    The impact of junction depth on vertical sidewall MOSFETs with embedded gate by Chih-Hao Kuo, Jyi-Tsong Lin, Tai-Yi Lee, Yi-Chuen Eng, Tzu-Feng Chang, Po-Hsieh Lin, Hsuan-Hsu Chen, Chih-Hung Sun, Hsien-Nan Chiu

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  15. 15
    Self-aligned SOI MOSFETs with Ω-shaped conductive layer and source/drain-tie

    Self-aligned SOI MOSFETs with Ω-shaped conductive layer and source/drain-tie by Jyi-Tsong Lin, Tzu-Feng Chang, Yi-Chuen Eng, Hsuan-Hsu Chen, Chih-Hao Kuo, Chih-Hung Sun, Po-Hiesh Lin, Hsien-Nan Chiu

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  16. 16
    A simulation study of source/drain-tie effects on characteristics of self-aligned π-shaped source/drain ultrathin SOI FETs

    A simulation study of source/drain-tie effects on characteristics of self-aligned π-shaped source/drain ultrathin SOI FETs by Yi-Chuen Eng, Jyi-Tsong Lin, Tzu-Feng Chang, Chih-Hao Kuo, Po-Hsieh Lin, Chih-Hung Sun, Hsien-Nan Chiu, Hsuan-Hsu Chen

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