Search Results - Hyun-geun Byun

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  1. 1
    Enhanced write performance of a 64-mb phase-change random access memory

    Enhanced write performance of a 64-mb phase-change random access memory by OH, Hyung-Rok, CHO, Beak-Hyung, JEONG, Gi-Tae, JEONG, Hong-Sik, KIM, Kinam, WOO YEONG CHO, KANG, Sangbeom, CHOI, Byung-Gil, KIM, Hye-Jin, KIM, Ki-Sung, KIM, Du-Eung, KWAK, Choong-Keun, BYUN, Hyun-Geun

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  2. 2
    An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology

    An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology by Sohn, K., Hyun-Sun Mo, Young-Ho Suh, Hyun-Geun Byun, Hoi-Jun Yoo

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  3. 3
    Temperature‐Adaptive Back‐Bias Voltage Generator for an RCAT Pseudo SRAM

    Temperature‐Adaptive Back‐Bias Voltage Generator for an RCAT Pseudo SRAM by Son, Jong‐Pil, Byun, Hyun‐Geun, Jun, Young‐Hyun, Kim, Kinam, Kim, Soo‐Won

    Published in ETRI journal
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  4. 4
    A 0.1-μm 1.8-V 256-Mb phase-change random access memory (PRAM) with 66-MHz synchronous burst-read operation

    A 0.1-μm 1.8-V 256-Mb phase-change random access memory (PRAM) with 66-MHz synchronous burst-read operation by KANG, Sangbeom, WOO YEONG CHO, YU HWAN RO, KIM, Suyeon, HA, Choong-Duk, KIM, Ki-Sung, KIM, Young-Ran, KIM, Du-Eung, KWAK, Choong-Keun, BYUN, Hyun-Geun, JEONG, Gitae, JEONG, Hongsik, CHO, Beak-Hyung, KIM, Kinam, SHIN, Yunsueng, LEE, Kwang-Jin, LEE, Chang-Soo, OH, Hyung-Rok, CHOI, Byung-Gil, QI WANG, KIM, Hye-Jin, PARK, Mu-Hui

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  5. 5
    A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM

    A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM by Cho, Uk-Rae, Kim, Tae-Hyoung, Yoon, Yong-Jin, Lee, Jong-Cheol, Bae, Dae-Gi, Kim, Nam-Seog, Kim, Kang-Young, Son, Young-Jae, Yang, Jeong-Suk, Sohn, Kwon-Il, Kim, Sung-Tae, Lee, In-Yeol, Lee, Kwang-Jin, Kang, Tae-Gyoung, Kim, Su-Chul, Ahn, Kee-Sik, Byun, Hyun-Geun

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  6. 6
    Voltage‐Mode 1.5 Gbps Interface Circuits for Chip‐to‐Chip Communication

    Voltage‐Mode 1.5 Gbps Interface Circuits for Chip‐to‐Chip Communication by Lee, Kwang‐Jin, Kim, Tae‐Hyoung, Cho, Uk‐Rae, Byun, Hyun‐Geun, Kim, Suki

    Published in ETRI journal
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  7. 7
    Voltage-Mode 1.5 Gbps Interface Circuits for Chip-to-Chip Communication

    Voltage-Mode 1.5 Gbps Interface Circuits for Chip-to-Chip Communication by Lee, Kwang-Jin, Kim, Tae-Hyoung, Cho, Uk-Rae, Byun, Hyun-Geun, Kim, Su-Ki

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  8. 8
    A 0.1- \mu} 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

    A 0.1- \mu} 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation by Sangbeom Kang, Woo Yeong Cho, Beak-Hyung Cho, Kwang-Jin Lee, Chang-Soo Lee, Hyung-Rok Oh, Byung-Gil Choi, Qi Wang, Hye-Jin Kim, Mu-Hui Park, Yu Hwan Ro, Suyeon Kim, Choong-Duk Ha, Ki-Sung Kim, Young-Ran Kim, Du-Eung Kim, Choong-Keun Kwak, Hyun-Geun Byun, Gitae Jeong, Hongsik Jeong, Kinam Kim, Shin, Y.

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  9. 9
    Temperature-Adaptive Back-Bias Voltage Generator for an RCAT Pseudo SRAM

    Temperature-Adaptive Back-Bias Voltage Generator for an RCAT Pseudo SRAM by Son, Jong-Pil, Byun, Hyun-Geun, Jun, Young-Hyun, Kim, Ki-Nam, Kim, Soo-Won

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  10. 10
    A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy

    A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy by Sohn, Kyomin, Suh, Young-Ho, Son, Young-Jae, Yim, Dae-Sik, Kim, Kang-Young, Bae, Dae-Gi, Kang, Ted, Lim, Hoon, Jung, Soon-Moon, Byun, Hyun-Geun, Jun, Young-Hyun, Kim, Kinam

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  11. 11
    Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application

    Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application by Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun

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  12. 12
    A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch

    A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch by Tae-Hyoung Kim, Uk-Rae Cho, Hyun-Geun Byun

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  13. 13
    A pseudo-differential CMOS receiver insensitive to input common mode level

    A pseudo-differential CMOS receiver insensitive to input common mode level by Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun

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  14. 14
    A Digitally Controlled Oscillator for Low Jitter All Digital Phase Locked Loops

    A Digitally Controlled Oscillator for Low Jitter All Digital Phase Locked Loops by Kwang-Jin Lee, Seung-Hun Jung, Yun-Jeong Kim, Chul Kim, Suki Kim, Uk-Rae Cho, Choong-Guen Kwak, Hyun-Geun Byun

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  15. 15
    A 0.7fJ/bit/search, 2.2ns search time hybrid type TCAM architecture

    A 0.7fJ/bit/search, 2.2ns search time hybrid type TCAM architecture by CHOI, Sungdae, SOHN, Kyomin, LEE, Min-Wuk, KIM, Sunyoung, CHOI, Hye-Mi, KIM, Donghyun, CHO, Uk-Rae, BYUN, Hyun-Geun, SHIN, Yun-Seung, YOO, Hoi-Jun

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  16. 16
    The effects of STI process parameters on the integrity of dual gate oxides

    The effects of STI process parameters on the integrity of dual gate oxides by Hoon Lim, Seung-Jae Lee, Jong-Mil Youn, Tae-Hong Ha, Jin-Ho Kim, Bong-Hyun Choi, Ki-Joon Kim, Ho-Jin Kim, Kyeong-Tae Kim, Hyun-Geun Byun

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  17. 17
    A 0.18-μm 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)

    A 0.18-μm 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM) by WOO YEONG CHO, CHO, Beak-Hyung, HWANG, Youngnam, AHN, Sujin, KOH, Gwan-Hyeob, JEONG, Gitae, JEONG, Hongsik, KIM, Kinam, CHOI, Byung-Gil, OH, Hyung-Rok, KANG, Sangbeom, KIM, Ki-Sung, KIM, Kyung-Hee, KIM, Du-Eung, KWAK, Choong-Keun, BYUN, Hyun-Geun

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  18. 18
    An autonomous SRAM with on-chip sensors in an 80nm double stacked cell technology

    An autonomous SRAM with on-chip sensors in an 80nm double stacked cell technology by Kyomin Sohn, Namjun Cho, Hyejung Kim, Kwanho Kim, Hyun-Sun Mo, Young-Ho Suh, Hyun-Geun Byun, Hoi-Jun Yoo

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  19. 19
    A SRAM Core Architecture with Adaptive Cell Bias Scheme

    A SRAM Core Architecture with Adaptive Cell Bias Scheme by Hak-soo Yu, Nam-Seog Kim, Young-Jae Son, Yong-Goel Kim, Hyo-Chang Kim, Uk-Rae Cho, Hyun-Geun Byun

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  20. 20
    A 0.18-/spl mu/m 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)

    A 0.18-/spl mu/m 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM) by Cho, Woo Yeong, Cho, Beak-Hyung, Byung-Gil Choi, Hyung-Rok Oh, Kang, Sangbeom, Ki-Sung, Kim, Kim, Kyung-Hee, Du-Eung, Kim, Kwak, Choong-Keun, Hyun-Geun Byun, Hwang, Youngnam, Ahn, S, Koh, Gwan-Hyeob, Jeong, Gitae, Jeong, Hongsik, Kim, Kinam

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