Search Results - Iesurum, Agata

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  1. 1
    Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs

    Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs by Iesurum, Agata, Manente, Davide, Padovan, Fabio, Bassi, Matteo, Bevilacqua, Andrea

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  2. 2
    A Stacking Technique for High-Swing Low-Phase Noise Class-C Oscillators Using Core Devices in Ultrascaled CMOS Technologies

    A Stacking Technique for High-Swing Low-Phase Noise Class-C Oscillators Using Core Devices in Ultrascaled CMOS Technologies by Tomasin, Lorenzo, Iesurum, Agata, Gobbo, Andrea, Neviani, Andrea, Bevilacqua, Andrea

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  3. 3
    A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time

    A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time by Dartizio, Simone M., Buccoleri, Francesco, Tesolin, Francesco, Avallone, Luca, Santiccioli, Alessio, Iesurum, Agata, Steffan, Giovanni, Cherniak, Dmytro, Bertulessi, Luca, Bevilacqua, Andrea, Samori, Carlo, Lacaita, Andrea L., Levantino, Salvatore

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  4. 4
    A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner

    A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner by Buccoleri, Francesco, Dartizio, Simone M., Tesolin, Francesco, Avallone, Luca, Santiccioli, Alessio, Iesurum, Agata, Steffan, Giovanni, Cherniak, Dmytro, Bertulessi, Luca, Bevilacqua, Andrea, Samori, Carlo, Lacaita, Andrea L., Levantino, Salvatore

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  5. 5
    A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs

    A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs by Grimaldi, Luigi, Iesurum, Agata, Boi, Giovanni, Versolatto, Fabio, Steffan, Giovanni, Padovan, Fabio, Koltsov, Heorhii, Bevilacqua, Andrea, Cherniak, Dmytro

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  6. 6
    A 68.6fsrms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching

    A 68.6fsrms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching by Dartizio, Simone Mattia, Buccoleri, Francesco, Tesolin, Francesco, Avallone, Luca, Santiccioli, Alessio, Iesurum, Agata, Steffan, Giovanni, Cherniak, Dmytro, Bertulessi, Luca, Bevilacqua, Andrea, Samori, Carlo, Lacaita, Andrea Leonardo, Levantino, Salvatore

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  7. 7
    A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler

    A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler by Buccoleri, Francesco, Dartizio, Simone M., Tesolin, Francesco, Avallone, Luca, Santiccioli, Alessio, Iesurum, Agata, Steffan, Giovanni, Bevilacqua, Andrea, Bertulessi, Luca, Cherniak, Dmytro, Samori, Carlo, Lacaita, Andrea L., Levantino, Salvatore

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