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Highly Optimized Nanocrystal-Based Split Gate Flash for High Performance and Low Power Microcontroller Applications
by
Yater, J
,
Hong, C
,
Kang, S.-T
,
Kolar, D
,
Min, B
,
Shen, J
,
Chindalore, G
,
Loiko, K
,
Winstead, B
,
Williams, S
,
Gasquet, H
,
Suhail, M
,
Broeker, K
,
Lepore, E
,
Hardell, A
,
Malloch, W
,
Syzdek, R
,
Chen, Y
,
Ju, Y
,
Kumarasamy, S
,
Liu, H
,
Lei, L
,
Indajang, B
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Design and Optimization of nanoCMOS devices using predictive atomistic physics-based process modeling
by
Colombeau, B.
,
Mok, K.R.C.
,
Yeong, S.H.
,
Benistant, F.
,
Indajang, B.
,
Tan, O.
,
Yang, B.
,
Li, Y.
,
Jaraiz, M.
,
Cowern, N.E.B.
,
Chu, S.
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Acceleration
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Arrays
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Boron
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Cmos Technology
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Design Optimization
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Electronics Industry
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Logic Gates
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Nanocrystals
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Pulp Manufacturing
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Simulated Annealing
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