Search Results - Iskander, Ramy

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  1. 1
    Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs

    Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs by Buccella, Pietro, Stefanucci, Camillo, Hao Zou, Moursy, Yasser, Iskander, Ramy, Sallese, Jean-Michel, Kayal, Maher

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  2. 2
    Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications

    Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications by Moursy, Yasser, Hao Zou, Khalil, Raouf, Iskander, Ramy, Tisserand, Pierre, Dieu-My Ton, Pasetti, Giuseppe, Louerat, Marie-Minerve

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  3. 3
    Using CAD Tool for Substrate Parasitic Modeling in Smart Power Technology

    Using CAD Tool for Substrate Parasitic Modeling in Smart Power Technology by Hao Zou, Moursy, Yasser, Iskander, Ramy, Steinmair, Alexander, Gensinger, Heimo, Seebacher, Ehrenfried, Chaput, Jean-Paul, Louerat, Marie-Minerve

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  4. 4
    Hierarchical sizing and biasing of analog firm intellectual properties

    Hierarchical sizing and biasing of analog firm intellectual properties by Iskander, Ramy, Louërat, Marie-Minerve, Kaiser, Andreas

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  5. 5
    Substrate noise modeling with dedicated CAD framework for smart power ICs

    Substrate noise modeling with dedicated CAD framework for smart power ICs by Hao Zou, Moursy, Yasser, Iskander, Ramy, Stefanucci, Camillo, Buccella, Pietro, Kayal, Maher, Sallese, Jean-Michel

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  6. 6
    Towards automatic diagnosis of minority carriers propagation problems in HV/HT automotive smart power ICs

    Towards automatic diagnosis of minority carriers propagation problems in HV/HT automotive smart power ICs by Moursy, Yasser, Hao Zou, Iskander, Ramy, Tisserand, Pierre, Dieu-My Ton, Pasetti, Giuseppe, Seebacher, Ehrenfried, Steinmair, Alexander, Gneiting, Thomas, Alius, Heidrun

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  7. 7
    Fast multidimensional optimization of analog circuits initiated by monodimensional global Peano explorations

    Fast multidimensional optimization of analog circuits initiated by monodimensional global Peano explorations by Malak, Akram, Li, Yao, Iskander, Ramy, Durbin, François, Javid, Farakh, Guebhard, Jean-Marc, Louërat, Marie-Minerve, Tissot, André

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  8. 8
    Automatic DC operating point computation and design plan generation for analog IPs

    Automatic DC operating point computation and design plan generation for analog IPs by Iskander, Ramy, Louërat, Marie-Minerve, Kaiser, Andreas

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  9. 9
    A structured DC analysis methodology for accurate verification of analog circuits

    A structured DC analysis methodology for accurate verification of analog circuits by Javid, Farakh, Iskander, Ramy, Louerat, Marie-Minerve, Durbin, Francois

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  10. 10
    Analog circuits sizing using bipartite graphs

    Analog circuits sizing using bipartite graphs by Javid, F., Iskander, R., Louerat, Marie-Minerve, Dupuis, D.

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  11. 11
    Automatic biasing point extraction and design plan generation for analog IPs

    Automatic biasing point extraction and design plan generation for analog IPs by Iskander, R., Kaiser, A., Louerat, M.M.

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  12. 12
    Modeling, design and verification platform using SystemC AMS

    Modeling, design and verification platform using SystemC AMS by Yao Li, Iskander, Ramy, Louerat, Marie-Minerve

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  13. 13
    A Python-based layout-aware analog design methodology for nanometric technologies

    A Python-based layout-aware analog design methodology for nanometric technologies by Youssef, S., Javid, F., Dupuis, D., Iskander, R., Louerat, M.

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  14. 14
    Synthesis of CMOS analog cells using AMIGO

    Synthesis of CMOS analog cells using AMIGO by Iskander, Ramy, Dessouky, Mohamed, Aly, Maie, Magdy, Mahmoud, Hassan, Noha, Soliman, Noha, Moussa, Sami

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  15. 15
    A unified platform for design and verification of mixed-signal systems based on SystemC AMS

    A unified platform for design and verification of mixed-signal systems based on SystemC AMS by Yao Li, Iskander, R., Javid, F., Louerat, M-M

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  16. 16
    Synthesis of CMOS analog cells using AMIGO

    Synthesis of CMOS analog cells using AMIGO by Iskander, R., Dessouky, M., Aly, M., Magdy, M., Hassan, N., Soliman, N., Moussa, S.

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  17. 17
    Simulation-based hierarchical sizing and biasing of analog firm IPs

    Simulation-based hierarchical sizing and biasing of analog firm IPs by Javid, F., Iskander, R., Louerat, M.-M.

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  18. 18
    Design and modeling of a successive approximation ADC for the electrostatic harvester of vibration energy

    Design and modeling of a successive approximation ADC for the electrostatic harvester of vibration energy by Khalil, R., Dudka, A., Galayko, D., Iskander, R., Basset, P.

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  19. 19
    A seamless representation for coupling transistor sizing with nanometric CMOS layout generation

    A seamless representation for coupling transistor sizing with nanometric CMOS layout generation by Youssef, S., Javid, F., Dupuis, D., Iskander, R., Louerat, M.

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  20. 20
    Automatic stress effects computation based on a layout generation tool for analog IC

    Automatic stress effects computation based on a layout generation tool for analog IC by Youssef, S., Dupuis, D., Iskander, R., Louerat, M-M

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