Search Results - Itocazu, V T

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  1. 1
    Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias

    Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias by Itocazu, V T, Almeida, L M, Sonnenberg, V, Agopian, P G D, Barraud, S, Vinet, M, Faynot, O, Martino, J A

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  2. 2
    Comparison between nMOS and pMOS Omega-gate nanowire down to 10nm width as a function of back gate bias

    Comparison between nMOS and pMOS Omega-gate nanowire down to 10nm width as a function of back gate bias by Itocazu, V. T., Almeida, L. M., Sonnenberg, V., Agopian, P. G. D., Barraud, S., Vinet, M., Faynot, O., Martino, J. A.

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  3. 3
    Comparison between nMOS and pMOS -gate nanowire down to 10 nm width as a function of back gate bias

    Comparison between nMOS and pMOS -gate nanowire down to 10 nm width as a function of back gate bias by Itocazu, V T, Almeida, L M, Sonnenberg, V, Agopian, P G D, Barraud, S, Vinet, M, Faynot, O, Martino, J A

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  4. 4
    Threshold Voltage Modeling for Dynamic Threshold UTBB SOI in Different Operation Modes

    Threshold Voltage Modeling for Dynamic Threshold UTBB SOI in Different Operation Modes by Itocazu, Vitor Tatsuo, Sasaki, Katia Regina Akemi, Manini, Matheus Barros, Sonnenberg, Victor, Martino, Joao Antonio, Simoen, Eddy, Claeys, Cor

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  5. 5
    Influence of High Temperature on UTBB SOI nMOSFETs with and without Ground Plane

    Influence of High Temperature on UTBB SOI nMOSFETs with and without Ground Plane by Sonnenberg, Victor, Itocazu, Vitor T., Martino, João Antonio, Simoen, Eddy R., Claeys, Cor

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  6. 6
    Analysis of the Silicon Film Thickness and the Ground Plane Influence on Ultra Thin Buried Oxide SOI nMOSFETs

    Analysis of the Silicon Film Thickness and the Ground Plane Influence on Ultra Thin Buried Oxide SOI nMOSFETs by Itocazu, V. T., Sonnenberg, V., Simoen, E., Claeys, C., Martino, J. A.

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  7. 7
    Analog parameters on pMOS SOI Ω-gate nanowire down to 10 nm width for different back gate bias

    Analog parameters on pMOS SOI Ω-gate nanowire down to 10 nm width for different back gate bias by Itocazu, V. T., Sonnenberg, V., Martino, J. A., Barraud, S., Vinet, M., Faynot, O.

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