A 1.6Gb/s/pin double-data-rale SDRAM with wave-pipelined CAS latency control by LEE, Sang-Bo, JANG, Seong-Jin, HEO, Hyoung-Jo, SHIN, Won-Hwa, LEE, Jong-Soo, PARK, Yun-Sik, KIM, Seok-Jung, JANG, Young-Uk, HWANG, Seok-Won, JUN, Young-Hyun, CHO, Soo-In, KWAK, Jin-Seok, HWANG, Sang-Jun, CHO, Seong-Ho, PARK, Min-Sang, LEE, Ho-Kyoung, LEE, Woo-Jin, LEE, Yu-Rim, CHO, Young-Cheol

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