Search Results - Jahinuzzaman, Shah

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  1. 1
    Soft Error Rate Improvements in 14-nm Technology Featuring Second-Generation 3D Tri-Gate Transistors

    Soft Error Rate Improvements in 14-nm Technology Featuring Second-Generation 3D Tri-Gate Transistors by Seifert, Norbert, Jahinuzzaman, Shah, Velamala, Jyothi, Ascazubi, Ricardo, Patel, Nikunj, Gill, Balkaran, Basile, Joseph, Hicks, Jeffrey

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  2. 2
    An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs

    An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs by Jahinuzzaman, S.M., Sharifkhani, M., Sachdev, M.

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  3. 3
    Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets

    Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets by Seifert, Norbert, Jahinuzzaman, Shah, Velamala, Jyothi, Patel, Nikunj

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  4. 4
    A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs

    A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs by Sharifkhani, M, Rahiminejad, E, Jahinuzzaman, S M, Sachdev, M

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  5. 5
    Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC

    Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC by Jahinuzzaman, S.M., Shah, J.S., Rennie, D.J., Sachdev, M.

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  6. 6
    A read-decoupled gated-ground SRAM architecture for low-power embedded memories

    A read-decoupled gated-ground SRAM architecture for low-power embedded memories by Hussain, Wasim, Jahinuzzaman, Shah M.

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  7. 7
    A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability

    A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability by Jahinuzzaman, S.M., Rennie, D.J., Sachdev, M.

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  8. 8
    Threshold voltage instability of amorphous silicon thin-film transistors under constant current stress

    Threshold voltage instability of amorphous silicon thin-film transistors under constant current stress by Jahinuzzaman, Shah M., Sultana, Afrin, Sakariya, Kapil, Servati, Peyman, Nathan, Arokia

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  9. 9
    Soft Error Susceptibilities of 22 nm Tri-Gate Devices

    Soft Error Susceptibilities of 22 nm Tri-Gate Devices by Seifert, N., Gill, B., Jahinuzzaman, S., Basile, J., Ambrose, V., Quan Shi, Allmon, R., Bramnik, A.

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  10. 10
    TSPC-DICE: A single phase clock high performance SEU hardened flip-flop

    TSPC-DICE: A single phase clock high performance SEU hardened flip-flop by Jahinuzzaman, S M, Islam, R

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  11. 11
    On the efficacy of using proton beams for estimating neutron-induced soft error rates

    On the efficacy of using proton beams for estimating neutron-induced soft error rates by Jahinuzzaman, Shah, Seifert, Norbert, Sekwao, Samwel, Neale, Adam

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  12. 12
    Correlating low energy neutron SER with broad beam neutron and 200 MeV proton SER for 22nm CMOS Tri-Gate devices

    Correlating low energy neutron SER with broad beam neutron and 200 MeV proton SER for 22nm CMOS Tri-Gate devices by Jahinuzzaman, S., Gill, B., Ambrose, V., Seifert, N.

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  13. 13
    A multiword based high speed ECC scheme for low-voltage embedded SRAMS

    A multiword based high speed ECC scheme for low-voltage embedded SRAMS by Jahinuzzaman, S., Shakir, T., Lubana, S., Shah, J.S., Sachdev, M.

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  14. 14
    Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model

    Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model by Jahinuzzaman, S.M., Sharifkhani, M., Sachdev, M.

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  15. 15
    Soft error robust impulse and TSPC flip-flops in 90nm CMOS

    Soft error robust impulse and TSPC flip-flops in 90nm CMOS by Jahinuzzaman, Shah M., Rennie, David J., Sachdev, Manoj

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