A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging by Mistry, K., Chau, R., Choi, C.-H., Ding, G., Fischer, K., Ghani, T., Grover, R., Han, W., Hanken, D., Hattendorf, M., He, J., Allen, C., Hicks, J., Huessner, R., Ingerly, D., Jain, P., James, R., Jong, L., Joshi, S., Kenyon, C., Kuhn, K., Lee, K., Auth, C., Liu, H., Maiz, J., McIntyre, B., Moon, P., Neirynck, J., Pae, S., Parker, C., Parsons, D., Prasad, C., Pipes, L., Beattie, B., Prince, M., Ranade, P., Reynolds, T., Sandford, J., Shifren, L., Sebastian, J., Seiple, J., Simon, D., Sivakumar, S., Smith, P., Bergstrom, D., Thomas, C., Troeger, T., Vandervoorn, P., Williams, S., Zawadzki, K., Bost, M., Brazier, M., Buehler, M., Cappellani, A.

Request full text

A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size by Natarajan, S., Agostinelli, M., Akbar, S., Bost, M., Bowonder, A., Chikarmane, V., Chouksey, S., Dasgupta, A., Fischer, K., Fu, Q., Ghani, T., Giles, M., Govindaraju, S., Grover, R., Han, W., Hanken, D., Haralson, E., Haran, M., Heckscher, M., Heussner, R., Jain, P., James, R., Jhaveri, R., Jin, I., Kam, H., Karl, E., Kenyon, C., Liu, M., Luo, Y., Mehandru, R., Morarka, S., Neiberg, L., Packan, P., Paliwal, A., Parker, C., Patel, P., Patel, R., Pelto, C., Pipes, L., Plekhanov, P., Prince, M., Rajamani, S., Sandford, J., Sell, B., Sivakumar, S., Smith, P., Song, B., Tone, K., Troeger, T., Wiedemer, J., Yang, M., Zhang, K.

Request full text