Search Results - Jenlung Liu

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  1. 1
    15.2 A 0.012mm2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider

    15.2 A 0.012mm2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider by Jenlung Liu, Tae-Kwang Jang, Yonghee Lee, Jungeun Shin, Seunghoon Lee, Taeik Kim, Jaejin Park, Hojin Park

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  2. 2
    A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS

    A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS by Jenlung Liu, Sehyung Jeon, Tae-Kwang Jang, Dohyung Kim, Jihyun Kim, Jaejin Park, Hojin Park

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  3. 3
    A 0.004mm2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications

    A 0.004mm2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications by Jong-Phil Hong, Sung-Jin Kim, Jenlung Liu, Nan Xing, Tae-Kwang Jang, Jaejin Park, Jihyun Kim, Taeik Kim, Hojin Park

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  4. 4
    A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR

    A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR by Jaejin Park, Liu, J.F., Carley, L.R., Yue, C.P.

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  5. 5
    A Sub-1V, 1.6mW, 2.06GHz clock generator for mobile SoC applications in 32nm CMOS

    A Sub-1V, 1.6mW, 2.06GHz clock generator for mobile SoC applications in 32nm CMOS by Liu, F J, Sehyung Jeon, Tae-Kwang Jang, Dohyung Kim, Jihyun Kim, Jaejin Park, Byeong-Ha Park

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