Search Results - Jeong-Dong Choe

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  1. 1
    Characteristics of the full CMOS SRAM cell using body-tied TG MOSFETs (bulk FinFETs)

    Characteristics of the full CMOS SRAM cell using body-tied TG MOSFETs (bulk FinFETs) by Tai-Su Park, Hye Jin Cho, Jeong Dong Choe, Sang Yeon Han, Donggun Park, Kinam Kim, Yoon, E., Jong-Ho Lee

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  2. 2
    Synchronous Pulse Plasma Operation upon Source and Bias Radio Frequencys for Inductively Coupled Plasma for Highly Reliable Gate Etching Technology

    Synchronous Pulse Plasma Operation upon Source and Bias Radio Frequencys for Inductively Coupled Plasma for Highly Reliable Gate Etching Technology by Tokashiki, Ken, Cho, Hong, Banna, Samer, Lee, Jeong-Yun, Shin, Kyoungsub, Todorow, Valentin, Kim, Woo-Seok, Bai, KeunHee, Joo, Sukho, Choe, Jeong-Dong, Ramaswamy, Kartik, Agarwal, Ankur, Rauf, Shahid, Collins, Ken, Choi, SangJun, Cho, Han, Kim, Hyun Joong, Lee, Changhun, Lymberopoulos, Dimitris, Yoon, Junho, Han, Woosung, Moon, Joo-Tae

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  3. 3
    Characteristics of body-tied triple-gate pMOSFETs

    Characteristics of body-tied triple-gate pMOSFETs by Tai-Su Park, Hye Jin Cho, Jeong Dong Choe, Il Hwan Cho, Donggun Park, Yoon, E., Jong Ho Lee

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  4. 4
    Fin-Type Field-Effect Transistor NAND Flash with Nitride/Silicon Nanocrystal/Nitride Hybrid Trap Layer

    Fin-Type Field-Effect Transistor NAND Flash with Nitride/Silicon Nanocrystal/Nitride Hybrid Trap Layer by Choe, Jeong-Dong, Lee, Se-Hoon, Lee, Jong Jin, Cho, Eun Suk, Ahn, Youngjoon, Choi, Byoung Yong, Sung, Suk Kang, No, Jintae, Chung, Ilsub, Park, Kyucharn, Park, Donggun

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  5. 5
    Twin SONOS memory with 30-nm storage nodes under a merged gate fabricated with inverted sidewall and damascene process

    Twin SONOS memory with 30-nm storage nodes under a merged gate fabricated with inverted sidewall and damascene process by Yong Kyu Lee, Ki Whan Song, Jae Woong Hyun, Jong Duk Lee, Byung-Gook Park, Sung Taeg Kang, Jeong Dong Choe, Sang Yeon Han, Jeong Nam Han, Sung Woo Lee, Kwon, O.I., Chung, C., Donggun Park, Kinam Kim

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  6. 6
    A 22-nm damascene-gate MOSFET fabrication with 0.9-nm EOT and local channel implantation

    A 22-nm damascene-gate MOSFET fabrication with 0.9-nm EOT and local channel implantation by Jeong-Dong Choe, Chang-Sub Lee, Sung-Ho Kim, Sung-Min Kim, Shin-Ae Lee, Ju-Won Lee, Shin, Y.-G., Donggun Park, Kinam Kim

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  7. 7
    A partially insulated field-effect transistor (PiFET) as a candidate for scaled transistors

    A partially insulated field-effect transistor (PiFET) as a candidate for scaled transistors by Yeo, K.H., Oh, C.W., Kim, S.M., Kim, M.S., Lee, C.S., Lee, S.Y., Han, S.Y., Yoon, E.J., Cho, H.J., Lee, D.Y., Yoon, B.M., Rhee, H.S., Lee, B.C., Choe, J.D., Chung, I., Park, D., Kim, K.

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  8. 8
    Threshold Voltage Behavior of Body-Tied FinFET (OMEGA MOSFET) with Respect to Ion Implantation Conditions

    Threshold Voltage Behavior of Body-Tied FinFET (OMEGA MOSFET) with Respect to Ion Implantation Conditions by Park, Tai-su, Cho, Hye Jin, Choe, Jeong Dong, Park, Donggun, Yoon, Euijoon, Lee, Jong-Ho

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  9. 9
    Vertical Structure NAND flash array integration with paired FinFET multi-bit scheme for high-density NAND flash memory application

    Vertical Structure NAND flash array integration with paired FinFET multi-bit scheme for high-density NAND flash memory application by June-Mo Koo, Tae-Eung Yoon, Taehee Lee, Sungjae Byun, Young-Gu Jin, Wonjoo Kim, Sukpil Kim, Jongbong Park, Junseok Cho, Jeong-Dong Choe, Choong-Ho Lee, Jong Jin Lee, Je-Woo Han, Yunseung Kang, Sangjun Park, Byoungho Kwon, Yong-Ju Jung, Inkyoung Yoo, Yoondong Park

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  10. 10
    Hybrid ALD-SiN/Si-nanocrystals/ALD-SiN FinFET device with large P/E window for MLC NAND Flash memory application

    Hybrid ALD-SiN/Si-nanocrystals/ALD-SiN FinFET device with large P/E window for MLC NAND Flash memory application by Jeong-Dong Choe, Se-Hoon Lee, Young Joon Ahn, Donghoon Jang, Young-Bae Yoon, Jong Jin Lee, Ilsub Chung, Kyucharn Park, Donggun Park

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  11. 11
    Lateral integration of partially insulated and bulk MOSFETs using partial SOI process

    Lateral integration of partially insulated and bulk MOSFETs using partial SOI process by Sung Hwan Kim, Chang Woo Oh, Kyoung Hwan Yeo, Dong Uk Choi, Min Sang Kim, Sung Min Kim, Jeong Dong Choe, Jeongnam Han, Young-Pil Kim, Dong-Won Kim, Donggun Park, Byung-Il Ryu

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  12. 12
    Fin width scaling criteria of body-tied FinFET in sub-50 nm regime

    Fin width scaling criteria of body-tied FinFET in sub-50 nm regime by Hye Jin Cho, Jeong Dong Choe, Ming Li, Jin Young Kim, Sung Hoon Chung, Chang Woo Oh, Eun-Jung Yoon, Dong-Won Kim, Donggun Park, Kinam Kim

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  13. 13
    Fabrication and characteristics of P -channel silicon-oxide-nitride-oxide-silicon flash memory device based on bulk fin shaped field effect transistor structure

    Fabrication and characteristics of P -channel silicon-oxide-nitride-oxide-silicon flash memory device based on bulk fin shaped field effect transistor structure by Cho, Il Hwan, Park, Tai-Su, Choe, Jeong Dong, Cho, Hye Jin, Park, Donggun, Shin, Hyungcheol, Park, Byung-Gook, Lee, Jong Duk, Lee, Jong-Ho

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  14. 14
    Improved Bake Retention Characteristic of Recessed Charge Trap Flash (RCTF)

    Improved Bake Retention Characteristic of Recessed Charge Trap Flash (RCTF) by Lee, Se Hoon, Kim, Woo-Jung, Yoon, Young-Bae, Park, Kyucharn, Lee, Jong Jin, Jang, Donghoon, Choe, Jeong-Dong, Kim, Taeyong, Cho, Eun Suk, Park, Se Joon, Ahn, Young Joon, Hwang, Won

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  15. 15
    Improved post-cycling characteristic of FinFET NAND Flash

    Improved post-cycling characteristic of FinFET NAND Flash by Se Hoon Lee, Jong Jin Lee, Jeong-Dong Choe, Eun Suk Cho, Young Joon Ahn, Won Hwang, Taeyong Kim, Woo-Jung Kim, Young-Bae Yoon, Donghoon Jang, Jongryeol Yoo, Dongdae Kim, Kyucharn Park, Donggun Park, Byung-Il Ryu

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  16. 16
    The Vth controllability of 5nm body-tied CMOS FinFET

    The Vth controllability of 5nm body-tied CMOS FinFET by Hye Jin Cho, Jeong Dong Choe, Jeongnam Han, Dongchan Kim, Heungsik Park, Doohoon Goo, Ming Li, Chang Woo Oh, Dong-Won Kim, Tae Yong Kim, Choong-Ho Lee, Donggun Park, Kinam Kim, Byung-Il Ryu

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  17. 17
    Transistor test structures for leakage current analysis of partial SOI

    Transistor test structures for leakage current analysis of partial SOI by KYOUNG HWAN YEO, CHANG WOO OH, KIM, Dong-Won, PARK, Donggun, KIM, Kinam, KIM, Sung-Min, KIM, Min-Sang, LEE, Sung-Young, MING LI, CHO, Hye-Jin, YOON, Eun-Jung, KIM, Sung-Hwan, CHOE, Jeong-Dong

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  18. 18
    Partially-insulated MOSFET (PiFET) and Its Application to DRAM Cell Transistor

    Partially-insulated MOSFET (PiFET) and Its Application to DRAM Cell Transistor by Oh, Chang-Woo, Kim, Sung-Hwan, Yeo, Kyoung-Hwan, Kim, Sung-Min, Kim, Min-Sang, Choe, Jeong-Dong, Kim, Dong-Won, Park, Dong-Gun

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  19. 19
    Partially-insulated MOSFET (PiFET) and Its Application to DRAM Cell Transistor

    Partially-insulated MOSFET (PiFET) and Its Application to DRAM Cell Transistor by Chang Woo Oh, Sung Hwan Kim, Kyoung Hwan Yeo, Sung Min Kim, Min Sang Kim, Jeong-Dong Choe, Dong-Won Kim, Donggun Park

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  20. 20
    Trap Layer Engineered FinFET NAND Flash with Enhanced Memory Window

    Trap Layer Engineered FinFET NAND Flash with Enhanced Memory Window by Ahn, Y., Choe, J.-D., Lee, J., Choi, D., Cho, E., Choi, B., Lee, S.-H., Sung, S.-K., Lee, C.-H., Cheong, S., Lee, D., Kim, S., Park, D., Ryu, B.-I.

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