Threshold Voltage Fluctuation by Random Telegraph Noise in Floating Gate nand Flash Memory String by JOE, Sung-Min, YI, Jeong-Hyong, PARK, Sung-Kye, SHIN, Hyungcheol, PARK, Byung-Gook, YOUNG JUNE PARK, LEE, Jong-Ho

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Position-Dependent Threshold-Voltage Variation by Random Telegraph Noise in nand Flash Memory Strings by Joe, Sung-Min, Yi, Jeong-Hyong, Park, Sung-Kye, Kwon, Hyuck-In, Lee, Jong-Ho

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Prediction of data retention time distribution of DRAM by physics-based statistical Simulation by Seonghoon Jin, Jeong-Hyong Yi, Jae Hoon Choi, Dae Gwan Kang, Park, Y.J., Hong Shick Min

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A New Direct Evaluation Method to Obtain the Data Retention Time Distribution of DRAM by JIN, Seonghoon, MYOUNG JIN LEE, YI, Jeong-Hyong, JAE HOON CHOI, DAE GWAN KANG, CHUNG, In-Young, YOUNG JUNE PARK, HONG SHICK MIN

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Numerical analysis of deep-trap behaviors on retention time distribution of DRAMs with negative wordline bias by Jeong-Hyong Yi, Sung-Kye Park, Park, Y.-J., Hong Shick Min

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Hole Mobility Characteristics under Electrical Stress for Surface-Channel Germanium Transistors with High-κ Gate Stack by Yi, Jeong-Hyong, Oh, Saeroonter, Wong, H.-S. Philip

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An abnormal floating gate interference and a low program performance in 2y nm NAND flash devices by Eunmee Kwon, Dongyean Oh, Bonghoon Lee, Jeong-hyong Yi, Sangyong Kim, Gyuseog Cho, Sungkye Park, Jaehoon Choi

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Device degradation model for polysilicon-oxide-nitride-oxide-silicon (SONOS) based on anode hole fluence by Yi, Jeong-Hyong, Lee, Sang-Don, Ahn, Jin-Hong, Shin, Hyungcheol, Park, Young-June, Min, Hong Shick

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Device degradation model for stacked-ONO gate structure with using SONOS and MOS transistors by Jeong-Hyong Yi, Jin-Hong Ahn, Hyungcheol Shin, Young-June Park, Hong Shick Min

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Chip Level Reliability of MANOS Cells under Operating Conditions by Eun-Seok Choi, Se-Jun Kim, Soon-Ok Seo, Hyun-Seung Yoo, Kyoung-Hwan Park, Sung-Wook Jung, Se-Yun Lim, Han-Soo Joo, Gyo-Ji Kim, Sang-Bum Lee, Sang-Hyun Oh, Jae-Chul Om, Jeong-Hyong Yi, Seok-Kiu Lee

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Polarity-dependent device degradation in SONOS transistors due to gate conduction under nonvolatile memory operations by Yi, J.-H., Shin, H., Park, Y.-J., Min, H.S.

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Modeling of retention time distribution of DRAM cell using a Monte-Carlo method by JIN, Seonghoon, YI, Jeong-Hyong, JAE HOON CHOI, DAE GWAN KANG, YOUNG JUNE PARK, HONG SHICK MIN

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A 117-mm(2) 3.3-V only 128-Mb multilevel NAND flash memoryfor mass storage applications by Jung, Tae-Sung, Choi, Young-Joon, Suh, Kang-Deog, Suh, Byung-Hoon, Kim, Jin-Ki, Lim, Young-Ho, Koh, Yong-Nam, Park, Jong-Wook, Lee, Ki-Jong, Park, Jung-Hoon, Park, Kee-Tae, Kim, Jhang-Rae, Yi, Jeong-Hyong, Lim, Hyung-Kyu

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A 117-mm/sup 2/ 3.3-V only 128-Mb multilevel NAND flash memory for mass storage applications by Tae-Sung Jung, Young-Joon Choi, Kang-Deog Suh, Byung-Hoon Suh, Jin-Ki Kim, Young-Ho Lim, Yong-Nam Koh, Jong-Wook Park, Ki-Jong Lee, Jung-Hoon Park, Kee-Tae Park, Jhang-Rae Kim, Jeong-Hyong Yi, Hyung-Kyu Lim

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